本論文設計一碼長1024,碼率0.5的高速且高吞吐率之極化碼連續消除解碼電路架構。本論文使用管線式樹狀架構搭配預先運算處理單元並在最後一級的解碼端運用預先運算節點和前瞻式運算節點的方式大幅降低解碼延遲週期實現高吞吐率的效果。在硬體優化上，本論文在預先處理單元上提出基於對數似然比的2補數表示法設計，此設計相較於以往文獻使用的符號大小表示法更可以大幅降低運算時間和硬體面積。此外，本論文提出的預先運算節點結合f節點和g節點的運算並搭配極化碼中凍結位元的特性來改善解碼複雜度和運算時間。
本論文所提出碼長1024編碼速率0.5的連續消除極碼解碼器分別在Altera 的Stratix IV系列FPGA (EP4SGX530KH40C2)、TSMC 0.18 μm CMOS元件庫以及FreePDK 45 nm CMOS元件庫實現與驗證。在FPGA部分，工作頻率可以達到218.72 MHz以及具有146 Mbps的吞吐率，使用32342個暫存器和45685個LUT，晶片功率消耗為2.11W，與先前文獻中所提出的設計，工作頻率提升26.4%、吞吐量提升240%;若以Free PDK 45 nm CMOS元件庫合成，工作頻率可以達到892 MHz以及具有595 Mbps的吞吐率，而所耗費的邏輯閘數量為282.69 KGE，與先前文獻中所提出的設計，工作頻率和吞吐率皆提升19%並且硬體面積節省16.5%;若以TSMC 0.18 μm CMOS元件庫合成，工作頻率可以達到400 MHz以及具有267 Mbps的吞吐率，而所耗費的邏輯閘數量為336 K，與先前文獻中所提出的設計，工作頻率提升6%、吞吐率提升112%;以TSMC 0.18 μm CMOS元件庫進行post-layout模擬，工作頻率可以達到361 MHz以及具有241 Mbps的吞吐率，而所耗費的邏輯閘數量為384 K，晶片功率消耗為973 mW。

This thesis presents a successive cancellation decoder architecture with high speed and high throughput features for a rate 0.5, length 1024 polar code. This work uses the pipelined tree architecture with pre-processing units and uses pre-computing nodes and the look-ahead computing nodes in the last stage of the decoder to largely reduce the decoding latency and achieve high throughput rate. In addition, from the hardware-optimizing aspect, we propose an algorithm for the pre-processing units based on 2’s complement representation of logarithmic likelihood ratio. It can significantly reduce the hardware area and the critical path length compared with using the sign-magnitude representation in previous state-of-the-art decoders. Moreover, the pre-computation node designed in this work combines the operations of f-node and g-node with the characteristics of frozen bit in the polar code to lower the decoding complexity and the critical path length.
The decoder is realized and verified on an Altera Stratix IV series FPGA (EP4SGX530KH40C2), as well as in TSMC 0.18 μm cell library and FreePDK 45 nm cell library. On the Stratix IV FPGA, our decoder can operate at a clock frequency up to 218.72 MHz and a throughput rate of 146 Mbps. The resource used by the decoder includes 32,342 registers and 45,685 LUTs. The chip power consumption is 2.11W. Compared with the previous state-of-the-art decoder on the same platform, our decoder’s maximum operating frequency is increased by 26.4% and the throughput rate is increased by 240%. Synthesized in Free PDK’s 45 nm cell library, our decoder’s maximum operating frequency can reach 892 MHz and maximum throughput rate can reach 595 Mbps. The total gate count is approximately 282.69K. Compared with the previous state-of-the-art decoder, our decoder’s maximum operating frequency and throughput rate are increased by 19%. The total gate count is saved by 16.5%. Synthesized in TSMC’s 0.18 μm cell library, our decoder’s maximum operating frequency can reach 400 MHz and maximum throughput rate can reach 267 Mbps. The total gate count is approximately 336K. Compared with the previous state-of-the-art decoder, our decoder’s maximum operating frequency is increased by 6% and maximum throughput rate is increased by 112%. In the post-layout simulation using TSMC’s 0.18 μm cell library, our decoder’s maximum operating frequency can reach 361 MHz and maximum throughput rate can reach 241 Mbps. The total gate count is approximately 384K. The chip power consumption is 973mW.

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