本篇論文提出一種應用於5G的極化碼(Polar Code)置信度傳播位元翻轉解碼器，並用FPGA與超大型積體電路設計與實現，硬體架構上以碼率(0.5)設計多種碼長，主要目標為實現出置信度傳播翻轉解碼器，硬體架構以置信度傳播解碼減少解碼延遲為目標。以PE數量減少使用大量記憶體寫入讀取的解碼延遲，甚者可以使用標準化解碼因數(uniform factor graph)來降低硬體在設計上的複雜度。
本論文使用MATLAB作為軟體的模擬環境，以Xilinx Virtex7 FPGA開發板作為FPGA模擬環境，而設計電路之實現則是使用TSMC 40nm製程技術進行實作。

This paper proposes a code applied to 5G Polar Code Belief Propagation Flip d ecoder, designed and implemented with FPGA and VLSI, the code rate architectures (0.5) to design many code Long, the main goal is to realize the Belief Propagation Flip d ecoder, and the hardware architecture aims at reducing the decoding delay by Belief propagation decoding. The number of PEs is used to reduce the decoding delay of writing and reading using a large amount of memory, and even a standardized decoding factor by uniform factor graph can be used to reduce the complexity of hardware design.
This paper uses MATLAB as the software simulation environment, Xilinx Virtex7 FPGA development board as the FPGA simulation environment, and the realization of the design circuit is implemented using TSMC 40nm process technology.

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