本篇論文提出了一種高吞吐量(High Throughput)置信度傳播解碼器(belief propagation decoder)並且使用超大型積體電路(very-large-scale integration)和FPGA進行設計與實現，在硬體架構上置信度傳播解碼器是以平行化的方式來增加解碼的效率，但每次進行遞迴運算時會有許多閒置的硬體單元在等待運算，因此如果使用特殊的排列架構使解碼器在進行疊代運算時以pipeline的方式進行資料傳送就可以提高硬體的使用率，藉此來增加解碼器的吞吐量，為了完成此設計本篇架構使用一致性因子圖(uniform factor graph)來簡化硬體架構設計的複雜性，並以此設計完成流水線架構使其具有高吞吐量的特性。
本篇論文使用Matlab作為軟體環境來驗證演算法，並使用Virtex7 FPGA 做為硬體驗證平台，最後使用TSMC 40奈米製程實現積體電路設計。

This paper proposes a high throughput (High Throughput) belief propagation decoder and uses very-large-scale integration and FPGA for design and implementation.
In the hardware architecture, the belief propagation decoder is to increase the efficiency of decoding in a parallel manner. But every time we perform the recursive operation,There will be many idle hardware units waiting for calculations,therefore ,if use a special arrangement structure,the decoder will use the pipeline method for data transmission when performing iterative calculations, which can increase the utilization rate of the hardware to increase the throughput of the decoder, in order to complete this design, this paper uses a uniform factor graph to simplify the complexity of the hardware architecture design, and uses this design to complete the pipeline architecture to have high throughput characteristics.
This paper uses Matlab as the software environment to verify the algorithm, and Virtex7 FPGA as the hardware verification platform, and finally uses the TSMC 40nm process to realize the integrated circuit design.

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