錯誤修正碼與內建自我修復 (BISR) 技術被廣泛的用來改善記憶體良率與可靠度。而這兩個技術主要處理的錯誤與瑕疵分別為永久瑕疵 (硬錯誤) 與軟錯誤。在過去有許多研究探討如何使用錯誤修正碼與 BISR 同時修復硬錯誤與軟錯誤。然而，錯誤修正碼的保護能力用來修復硬錯誤會造成可靠度下降。為了解決此問題，在此論文提出結合硬體修復與錯誤修正碼提升嵌入式記憶體良率與可靠度 (ECC-enhanced BISR, EBISR) 技術，利用錯誤修正碼修復單錯誤故障，剩餘的故障再利用修復分析演算法使用備用元件取代。
在系統執行時，利用單錯誤修正雙錯誤偵測 (Single Error Correction Double Error Detection, SEC-DED) 碼偵測編碼字，當編碼字為無錯誤或 1 位元錯誤，則依照原本錯誤修正機制將資料正常輸出。若發生雙錯誤會將編碼字變補寫回記憶體後再讀出，比照原本編碼字判斷錯誤形態。判斷為一硬錯誤一軟錯誤或雙硬錯誤的情況，能將編碼字修正後讀出；若為雙軟錯誤，則會向下層記憶體讀取資料。而此技術能夠在系統運作的階段維持原本錯誤修正碼的可靠度。
我們實現了 EBISR的硬體架構，也利用模擬器去計算修復分析演算法的修復率與可靠度。實驗結果顯示我們提出的 EBISR 演算法能夠顯著的改善良率與可靠度。在 512 × 1248 × 39 大小的記憶體使用兩個備用行兩個備用列的修復率達到約 100%。可靠度在五十萬小時能夠維持在 94%。而增加的硬體成本占整個晶片不到 1% 之比率。

Error correction codes (ECC) and hard repair (built-in self-repair) techniques by using redundancies have been widely used for improving the yield and reliability of memories. The target faults of these two schemes are soft errors and permanent faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability since some of the ECC protection capability is used for repairing hard defects. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-on test and repair stage.
When the memory system is used on-line, the Single Error Correction Double Error Detection (SEC-DED) code is used to check if the read-out codeword is faulty. If the codeword is fault-free or contains at most one faulty bit, the data will be transferred correctly by the original error correction scheme. Otherwise, if the codeword contains two errors, the codeword will be complemented and written-back and then read-out to/from the memory. After the above operations, the read-out codeword is compared with the original codeword. If there is one hard-error and one soft error or two hard errors, the codeword could be corrected and read-out. However, if the codeword contains two soft errors, the correct codeword should be retrieved from the lower-level memory hierarchy. Techniques are proposed to maintain the original reliability during the on-line test and repair stage.
We also propose the corresponding hardware architecture of the EBISR scheme. A simulator is implemented to evaluate the repair rate and reliability. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly. We can achieve up to 100% repair rate for a 512 × 1248 × 39 memory with two spare rows and two spare columns. The reliability will achieve 94% after 0.5 million hours. The area overhead is less than 1%.

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