干擾錯誤和保留時間錯誤是3D-TLC閃存中的兩種主要錯誤類型。 隨著的P/E cycles增加，氧化層變薄。 因此，存儲在電池中的電荷變得更容易丟失，這將導致Vth發生負向偏移。 同時，由於FN隧道效應，也會使電壓的Vth正向偏移。 在本文中，我們提出RDER-FTL以適當利用讀干擾及保留時間錯誤讓這兩個效應互補，讓Vth平衡到其原始狀態。 實驗結果表明，採用我們的方案可以有效地將block erase count減少多達59％。

Disturbance error and retention time error are two main types of errors in 3D-TLC flash memory. As the endured P/E cycles increased, the oxide layer becomes thinner. Thus charges stored in the cell becomes easier to lose, which would cause Vth to drift negatively. In the meantime, the Vth of the cell will shift positively due to the FN tunnel effect. In this paper, we propose RDER-FTL to properly exploit these two complementary effects, aiming at balancing the Vth to its original state. The experiment results showed that applying our scheme could effectively reduce the block erase counts up to 59%.

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