由於可重組態系統架構具有低功耗以及高效能的優勢，可望成為下一代智慧型裝置使用的架構。為維持智慧型裝置的可攜性，如何配置工作以達到節省能源消耗以及利用硬體可重組特性節省所需可重組邏輯陣列面積成為重要的技術議題。本論文提出功耗感知的軟硬體協同排程與可重組工作管理框架，降低系統整體耗能，並利用執行時期的工作配置器決定硬體工作的可重組區域與占用時間，降低晶片所需面積。本論文提出的方法經過一系列實驗分析，發現在有限的可重組邏輯陣列晶片面積可達到較低的能源消耗與較高的工作滿足率。

Dynamic partial reconfigurable systems with a processor and a field-programmable gate array are promising innovations for meet the requirement of mobile embedded devices demonstrating low power consumption and high performance. However, with limited battery life and chip size, the energy consumption and area allocation are critical concerns for such systems. In this study, a energy-aware hardware/software partition is presented to minimize the system energy consumption, and contention-aware task allocation is presented to minimize the area requirement and response time. The energy efficiency and schedulability of the proposed methodology was evaluated using a series of workloads, and impressive results were obtained.

[1] Lattice, http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx,
Lattice iCE40 Ultra/UltraLite, 2015.
[2] XILINX, http://www.xilinx.com, Partial Reconfiguration User Guide, 2013.
[3] XILINX, http://www.xilinx.com, Partial Reconfiguration of Xilinx FPGAs Using
ISE Design Suite, 2012.
[4] E. Lぴubbers and M. Platzner, “Reconos: An operating system for dynamically
reconfigurable hardware,” in Dynamically Reconfigurable Systems, pp. 269–290,
Springer, 2010.
[5] X. Iturbe, K. Benkrid, C. Hong, A. Ebrahim, T. Arslan, and I. Martinez, “Runtime
scheduling, allocation, and execution of real-time hardware tasks onto xilinx fpgas
subject to fault occurrence,” International Journal of Reconfigurable Computing,
vol. 2013, 2013.
[6] S. G. Li, F. J. Feng, H. J. Hu, C. Wang, and D. Qi, “Hardware/software partitioning
algorithm based on genetic algorithm,” Journal of Computers, vol. 9, no. 6,
pp. 1309–1315, 2014.
[7] A. Mishra, D. Vakharia, A. J. Hati, and K. S. Raju, “Hardware software partitioning
of task graph using genetic algorithm,” in Recent Advances and Innovations in
Engineering (ICRAIE), 2014, pp. 1–5, IEEE, 2014.
[8] Y. Jing, J. Kuang, J. Du, and B. Hu, “Application of improved simulated annealing
optimization algorithms in hardware/software partitioning of the reconfigurable
system-on-chip,” in Parallel Computational Fluid Dynamics, pp. 532–540, Springer,
2014.
[9] Y. Su, C. XU, and Y. Qin, “A hw/sw partitioning algorithm for embedded security
systems,” Journal of Computational Information Systems, vol. 11, no. 1, pp. 237–
246, 2015.
[10] P. Liu, J. Wu, and Y. Wang, “Hybrid algorithms for hardware/software partitioning
and scheduling on reconfigurable devices,” Mathematical and Computer Modelling,
vol. 58, no. 1, pp. 409–420, 2013.
[11] W. Jigang, T. Srikanthan, and T. Jiao, “Algorithmic aspects for functional partitioning
and scheduling in hardware/software co-design,” Design Automation for Embedded
Systems, vol. 12, no. 4, pp. 345–375, 2008.
[12] H. Han, L. Wenju, W. Jigang, and L. Hui, “Framework for hw/sw partitioning and
scheduling on mpsocs,” in Computer and Information Application (ICCIA), 2010
International Conference on, pp. 182–185, IEEE, 2010.
[13] O. Souissi, R. B. Atitallah, A. Artiba, and S. E. Elmaghraby, “Optimization of runtime
mapping on heterogeneous cpu/fpga architectures,” in 9th International Conference
on Modeling, Optimization & SIMulation, 2012.
[14] J. A. Clemente, E. Perez Ramo, J. Resano, D. Mozos, and F. Catthoor, “Configuration
mapping algorithms to reduce energy and time reconfiguration overheads in
reconfigurable systems,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions
on, vol. 22, no. 6, pp. 1248–1261, 2014.
[15] Y. Li, Z. Jia, S. Xie, and F. Liu, “An hw reconfigurable node with novel scheduling
in an energy-harvesting environment,”
[16] X. Iturbe, K. Benkrid, T. Arslan, C. Hong, A. T. Erdogan, and I.Martinez, “Enabling
fpgas for future deep space exploration missions: Improving fault-tolerance and
computation density with r3tos,” in Adaptive Hardware and Systems (AHS), 2011
NASA/ESA Conference on, pp. 104–112, IEEE, 2011.
[17] Y. Lu, T. Marconi, K. Bertels, and G. Gaydadjiev, “Online task scheduling for the
fpga-based partially reconfigurable systems,” in Reconfigurable Computing: Architectures,
Tools and Applications, pp. 216–230, Springer, 2009.
[18] C. Hong, K. Benkrid, X. Iturbe, A. T. Erdogan, and T. Arslan, “An fpga task allocator
with preliminary first-fit 2d packing algorithms,” in Adaptive Hardware and Systems
(AHS), 2011 NASA/ESA Conference on, pp. 264–270, IEEE, 2011.
[19] C. Hong, K. Benkrid, X. Iturbe, A. Ebrahim, and T. Arslan, “Efficient on-chip task
scheduler and allocator for reconfigurable operating systems,” Embedded Systems
Letters, IEEE, vol. 3, no. 3, pp. 85–88, 2011.
[20] T. Marconi, Y. Lu, K. Bertels, and G. Gaydadjiev, “Online hardware task scheduling
and placement algorithm on partially reconfigurable devices,” in Reconfigurable
Computing: Architectures, Tools and Applications, pp. 306–311, Springer, 2008.
[21] P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, “T-trees: A tree-based representation for
temporal and three-dimensional floorplanning,” ACM Transactions on Design Automation
of Electronic Systems (TODAES), vol. 14, no. 4, p. 51, 2009.
[22] T. Marconi, Y. Lu, K. Bertels, and G. Gaydadjiev, “3d compaction: A novel
blocking-aware algorithm for online hardware task scheduling and placement on
2d partially reconfigurable devices,” in Reconfigurable Computing: Architectures,
Tools and Applications, pp. 194–206, Springer, 2010.
[23] X. Iturbe, K. Benkrid, T. Arslan, I. Martinez, and M. Azkarate, “Atb: Area-time
response balancing algorithm for scheduling real-time hardware tasks,” in Field-
Programmable Technology (FPT), 2010 International Conference on, pp. 224–232,
IEEE, 2010.
[24] C.-C. Kao, “Performance-oriented partitioning for task scheduling of parallel reconfigurable
architectures,” Parallel and Distributed Systems, IEEE Transactions on,
vol. 26, no. 3, pp. 858–867, 2015.
[25] XILINX, http://www.xilinx.com,MicroBlaze Processor Reference Guide, 2010.
[26] C. L. Liu and J. W. Layland, “Scheduling algorithms for multiprogramming in a
hard-real-time environment,” Journal of the ACM (JACM), vol. 20, no. 1, pp. 46–61,
1973.
[27] H. Chiueh, J. Draper, and J. Choma, Jr., “An efficient list scheduling algorithm for
time placement problem,” Computers and Electrical Engineering, pp. 285 – 298,
2007.
[28] D. Chang andM.Marek-Sadowska, “Partitioning sequential circuits on dynamically
reconfigurable fpgas,” Computers, IEEE Transactions on, vol. 48, no. 6, pp. 565–
578, 1999.
[29] R. P. Dick, D. L. Rhodes, and W. Wolf, “Tgff: task graphs for free,” in Proceedings
of the 6th international workshop on Hardware/software codesign, pp. 97–101,
IEEE Computer Society, 1998.
[30] P.-A. Hsiung, P.-H. Lu, and C.-W. Liu, “Energy efficient co-scheduling in dynamically
reconfigurable systems,” in Proceedings of the 5th IEEE/ACM international
conference on Hardware/software codesign and system synthesis, pp. 87–92, ACM,
2007.
[31] M. Yuan, Z. Gu, X. He, X. Liu, and L. Jiang, “Hardware/software partitioning and
pipelined scheduling on runtime reconfigurable fpgas,” ACM Transactions on Design
Automation of Electronic Systems (TODAES), vol. 15, no. 2, p. 13, 2010.
[32] P.-A. Hsiung, C.-H. Huang, J.-S. Shen, and C.-C. Chiang, “Scheduling and placement
of hardware/software real-time relocatable tasks in dynamically partially reconfigurable
systems,” ACM Transactions on Reconfigurable Technology and Systems
(TRETS), vol. 4, no. 1, p. 9, 2010.
[33] Task Graph Generator. http://sourceforge.net/projects/taskgraphgen/, 2013.
[34] K. S. Chatha and R. Vemuri, “Hardware-software codesign for dynamically reconfigurable
architectures,” in Field Programmable Logic and Applications, pp. 175–
184, Springer, 1999.