在很多應用例如lookup table，database，associative computing和gigabit Ethernet， 因為內容可定址記憶體提供平行的比對以降低搜索時間，所以經常被用來改良這些應用的搜尋速度。 不過，平行的比對總是消耗較多的功率。 在本篇論文裡，為節省更多的功率消耗因此提出一個新的Precomputation-Based Content Addressable Memory (PB-CAM) 架構，此方法是根據PB-CAM的設計而加以改良。雖然PB-CAM能藉由減少比對動作而降低功率消耗，然而原始特徵值擷取器的設計方法會大幅限制所減少的比對動作數量。所以本論文設計一個新的特徵值擷取方法”Block-XOR”來改進PB-CAM的效率。依數學分析顯示若是輸入資料長度是32位元，本篇論文的方法將可以節省到一半的比對次數。在實驗過程中，使用TSMC 0.18-μm，1.8V。為求精準，本論文使用Synopsys Nanosim 量測功率消耗。
由實驗結果顯示，當Block-XOR與Ones count皆採用標準的記憶體電路設計 (9 顆電晶體)，Block-XOR可以節省72%的功率消耗。甚至是讓Ones count 採用特殊的記憶體電路設計 (7顆電晶體)，本論文所提出的方法也可以節省33%功率。 這篇文章的主要的目的是提供理論和實際的證據證實Block-XOR PB-CAM系統能取得更進一步的功率減少，並且CAM記憶體單元電路設計不需要使用特別的設計。也就是說Block-XOR可以適用於更多種類的記憶體電路設計已達到設計者的需求並且額外的提供低功率的效果。

In many applications such as lookup table, database, associative computing and gigabit Ethernet, the content addressable memory (CAM) is often used to improve the application performance since CAM provides the parallel comparison to reduce search time. However, the parallel comparisons always consume a significant amount of power. In this paper, we propose a new precomputation-based content addressable memory (PB-CAM) structure for saving the CAM system power. Our approach is based on the PB-CAM. Although the PB-CAM can reduce the comparison operations to reduce power consumption by precomputation, it suffers from that the precomputation-based ones count approach limits the reduction amount of comparison operations. In this paper, we devise a Block-XOR approach to improve the efficiency of PB-CAM. The mathematic analysis shows that our approach can effectively reduce the average comparison number to 50% under 32 bits compared to ones count approach. Incidentally, the ones count is three times the area of our Block-XOR in the parameter extractor circuit. In the experiment, we use TSMC 0.18-μm to estimate the power by Synopsys Nanosim for accuracy. Compared to ones count approach, the experimental result shows that our approach achieves 72% average power reduction in the standard memory cell design (nine transistors). Furthermore, our Block-XOR with standard memory cell design consumes 33% power of ones count with special memory cell design (seven transistors) for its best case. Moreover, the special memory cell is not standard design and is only suitable for ones count approach. The major contribution of this paper is that we provided theoretical and practical proof to verify that our Block-XOR PB-CAM system can achieve further power reduction, and the CAM cell design does not need to use the special design. It implies that our approach is more flexible and adaptive to the general design. Further, due to invariable comparison operation number (constant delay of search operation), the Block-XOR PB-CAM system is even more suitable for real-time application.

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