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研究生: Ebrima Njie
Ebrima - Njie
論文名稱: 三維晶片之熱管理綜評
A Survey on Thermal-Aware Management in 3D ICs
指導教授: 陳雅淑
Ya-Shu Chen
口試委員: 謝仁偉
Jen-Wei Hsieh
陳筱青
Hsiao-Chin Chen
張原豪
Yuan-Hao Chang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 42
中文關鍵詞: non
外文關鍵詞: three-dimensional multicore chip, floorplanning, TSV placement, thermal-aware scheduling
相關次數: 點閱:214下載:1
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    Thermal issue have become one of the major concerns for three-dimensional multicore chips. In this study, we surveyed recent thermal management techniques for three-dimensional multicore chips. All representative related work are presented and compared through hardware-level thermal management and software-level thermal management. Hardware-level thermal management is focus on component floorplanning and TSV placement for hotspot distribution. Software-level thermal management apply thermal-aware task scheduling with dynamic voltage frequency scaling and dynamic power management for run-time heat dissipation. The objective of this study is to provide a broad knowledge and further insights of designing thermal-aware three-dimensional multicore chips.

    1 Introduction 2 System Model 2.1 Hardware Architectures 2.1.1 Multi-Core floorplanning 2.2 Thermal Model 2.3 Task Model 2.4 Basic Techniques for Dynamic Thermal Management (DTM) 2.4.1 Power State Machine (PSM) 2.4.2 Dynamic Voltage and Frequency Scaling (DVFS) 3 Hardware-level Thermal Management 3.1 Power Management Techniques for Specific Processor 3.2 Thermal-aware Placement 3.2.1 Floorplaning for Hot Spot Distribution 3.2.2 TSV Placement 3.3 Future Direction 4 Software-level Thermal Management 4.1 Performance Optimization under Thermal Constraints 3D multi-core processor chips 4.2 Peak Temperature Minimization under Performance Constraints for 3D multi-core processor chips 4.3 Performance and Peak Temperature Optimization for 3D multi-core processor chips 4.4 Future Direction 5 Conclusion

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