本論文針對SISO及 MIMO OFDM系統提出近似Linear Minimum Mean Square Error (LMMSE)通道估測演算法之設計與實現，我們分別探討通道自相關矩陣為單位矩陣及固定的RMS delay spread兩種情況，這兩種演算法都是以Least Square (LS)為基底加以建構且需要使用FFT輸出訊號的SNR來做運算。在SISO時，傳送端會發送兩筆資料相同的訓練符元到接收端，利用此特性可設計一個電路針對FFT輸出訊號的SNR做估測，然而在 MIMO時，天線1及2會分開傳送資料，無法使用兩筆訓練符元做SNR檢測。從模擬結果得知，通道自相關矩陣定義為單位矩陣的作法在SISO可以節省更多面積，Mean Square Error(MSE)及封包錯誤率的表現同樣比較好，在 MIMO也可節省不少面積，MSE及PER在13dB後也會優於固定delay spread的方法。本論文以此演算法為目標，採用Verilog硬體描述語言設計，利用Xilinx ISE進行合成，最後將電路實現於FPGA開發板上。

This thesis proposes the hardware design and implementation of a quasi-Linear Minimum Mean Square Error (LMMSE) channel estimation algorithm for SISO and MIMO OFDM systems. We discuss two cases of the channel autocorrelation matrix: identity matrix and fixed channel RMS delay spread. In both cases our method is based on the Least Squares (LS) algorithm and requires the SNR of the FFT output signal. For the SISO system, the transmitter sends two identical training symbols to the receiver, which allows the design of a circuit to estimate the SNR of the FFT output signal. However, for the MIMO system, the two identical training symbols are separately transmitted in both antennas and hence cannot perform SNR estimation. Simulation results show that, when the channel autocorrelation matrix is defined as an identity matrix, the proposed algorithm saves more area on the FPGA, and improves Mean Square Error (MSE) and Packet Error Rate (PER) performance. Moreover, for the MIMO system, it also reduces circuit area, and has better MSE and PER performance than the method with fixed RMS delay spread for SNR ≥ 13dB. Using Verilog HDL for design and Xilinx ISE for circuit synthesis, this thesis implements this algorithm on an FPGA development board.

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