本論文提出一適用於生理訊號感測應用之旁通切換循序漸進式類比數位轉換 器電路設計，為了完成低功耗前端感測電路(Analog-Front-End, AFE)，低功耗類比數位轉換器為必須之電路。此電路能將所感測到之類比電壓訊號轉換為數位輸出，以利後端訊號處理系統分析。在大多數的時間下，生理信號在長時間的狀態下其信號振幅較為微弱。因此在本論文中提出一旁通切換式換循序漸進式類比數位轉換器，並採用一新型動態逼近式比較器。利用電流相關器(Current Correlator) 之電流特性，將旁通信號及輸入信號之比較結果同時輸出，並利用輸出旁通信號決定是否進入旁通介面，以優化低電壓靈敏度的不同偵測信號應用的功率消耗。此次所設計的類比數位轉換器的原型晶片採用0.35 微米的互補式金氧半製程來實現，其面積大小為0.284mm2。當電源電壓為1.8 V 及0.9 V，採樣頻率為2kS/s 時，其量測結果的信號雜訊失真比率與無雜散動態範圍分別為37.74 dB 和42.68 dB，並實現了5.98 的有效位元數。當輸入為正弦信號時，類比數位轉換器消耗功率為303 nW。為了使循序漸進式類比數位轉換器的消耗功率降低，採用先進的製程是必須的。此外將電容陣列中的單位電容架構採用3D 電容架構，此電容架構能實現一單位電容容值1 fF，以減少切換功率。並提出一新型旁通切換循序漸進邏輯電路，減少了邏輯電路的數量以及轉換功率。此次所設計的類比數位轉換器的原型晶片採用0.18 微米的互補式金氧半製程來實現，其面積大小為0.041mm2。當電源電壓為0.6 V，採樣頻率為50kS/s 時，其量測結果的信號雜訊失真比率與無雜散動態範圍分別為56.9 dB 和68.7 dB，並實現了9.16 的有效位元數。當輸入為正弦信號時，類比數位轉換器消耗功率為114 nW。在旁路窗口尺寸為±32LSB 的情況下，設計的類比數位轉換器輸入一在經認證的商用模擬器產生的心電圖信號時僅消耗76 nW，此類比數位轉換器品質因數為2.66 fJ/conversion-step.。除了心電信號外，並針對人體的肌電信號和眼電信號轉換來進行數位化演示。在先進製程中將循序漸進式類比數位轉換器進行生理信號偵測，需將類比數位轉換器操作於低取樣速率下，這將會使漏電流影響類比數位轉換器的線性度。因此在本論文中提出一新型取樣開關與負壓產生器。採用一負壓產生器關閉拔靴帶式開關，並增加電組的阻值限制開關的漏電流及增加開關線性度。此外一新型3D 電容架構被採用於電容陣列，此3D 電容架構能增加輸入振幅及降低單位容值，其單位容值為0.47 fF。此次所設計的類比數位轉換器的原型晶片採用55 奈米的互補式金氧半製程來實現，其面積大小為0.01mm2。當電源電壓為0.6 V，採樣頻率為500kS/s 時，其後製成模擬結果的信號雜訊失真比率與無雜散動態範圍分別為58.35 dB 和73.4 dB，並實現了9.4 的有效位元數。當輸入為正弦信號時，類比數位轉換器消耗功率為285.9 nW。在旁路窗口尺寸為±32LSB 的情況下，設計的類比數位轉換器輸入一在經認證的商用模擬器產生的心電圖信號時僅消耗173nW，此類比數位轉換器品質因數為0.512 fJ/conversion-step。

The circuit design of a bypass switching SAR ADC suitable for physiological signal detection is proposed in this thesis. To finish a low power analog-front-end (AFE) circuit, a low power analog to the digital converter (ADC) is needed. The ADC can convert the sensed signal to a digital output for the back-end signal processing system. For most of the time, the biomedical signals exhibit weak amplitude and low frequency. Therefore, this thesis has proposed a bypass switching SAR ADC employing a newly proposed dynamic proximity comparator. By exploiting the current characteristics of a current correlator, the proposed comparator generates the bypass signal directly along with the polarity comparison result. The bypass window size can be adjusted to optimize the power reduction for different sensing applications with low voltage sensitivity. A prototyped chip including a proposed ADC has been designed and fabricated in a 0.35 um CMOS process occupying an area of 0.284 mm2. With a supply voltage of 1.8 V and 0.9 V at a sampling rate of 2kS/s, the measured signal-to-noise-distortion ratio and spurious free dynamic range are 37.74 dB and 42.68 dB, which are combined with the analog-front-end design, respectively, achieving an effective number of bits of 5.98. The ADC consumes the power of 303 nW while digitizing the sinusoidal input. To improve the SAR ADC power efficiency, adopting an advanced CMOS process change is needed. Besides, the unit capacitor in the employed capacitor arrays adopts the 3D-layer structure with a capacitance value of 1 fF to decrease the conversion power. A bypass-switching successive approximation logic circuit is adopted with a reduced number of logic gates as well as the switching power. A prototyped chip including a proposed ADC has been designed and fabricated in a 0.18 um CMOS process occupying an area of 0.041 mm2. With a supply voltage of 0.6 V and at a sampling rate of 50kS/s, the measured signal-to-noise-distortion ratio and spurious free dynamic range are 56.9 dB and 68.7 dB,
respectively, achieving an effective number of bits being 9.16. The ADC consumes a power of 114 nW while digitizing the sinusoidal inputs. With a bypass window size of ±32 LSBs, the designed ADC consumes only 76 nW when quantizing the full-scale electrocardiography signals that are generated from a certified commercial simulator, exhibiting a figure-of-merit of 2.66 fJ/conversion-step. For the biomedical sensing that resolves the SAR ADC operation in low frequency and leakage current issue in the advanced CMOS process, this thesis has proposed a newly bootstrapped sample and hold switch with negative voltage bias. By implementing a negative voltage bias to turn off the bootstrapped switch, the on resistor would be larger than the limitation switch leakage current and thereby increase the linearity. A newly 3D capacitor structure has been proposed to increase the ADC input swing range and decrease the capacitance value to 0.47 fF. A prototyped chip including a proposed ADC has been designed and fabricated in a 55 nm CMOS process occupying an area of 0.01 mm2. With a supply voltage of 0.6 V and at a sampling rate of 500kS/s, the simulated signal-to-noise distortion ratio and spurious free dynamic range are 58.35 dB and 73.4 dB, respectively, achieving an effective number of bits being 9.4. The ADC consumes a power of 285.9 nW while digitizing the sinusoidal inputs. With a bypass window size of _32 LSBs, the designed ADC consumes only 173 nW when quantizing the full-scale electrocardiography signals that are generated from a certified commercial simulator, exhibiting a figure-of merit of 0.512 fJ/conversion-step in the post layout simulation results.

[1] M. V. Elzakker, E. v. Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink, andB. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9 uW at 1 MS/s,” IEEEJournal of Solid–State Circuits, vol. 45, no. 5, pp. 1007–1015, 2010.
[2] T. Delbruck, “Bump circuits for computing similarity and dissimilarity of analogvoltage,” in IEEE Proceedings of the International Neural Network Society, pp. 475–479, Oct. 1991.
[3] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADCwith a monotonic capacitor switching procedure,” IEEE Journal of Solid–State Circuits,vol. 45, no. 4, pp. 731–740, 2010.
[4] G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “A 1-uW 10-bit 200-kS/s SARADC with a bypass window for biomedical applications,” IEEE Journal of Solid–State Circuits, vol. 47, no. 11, pp. 2783–2795, 2012.
[5] S.-H. Wan, C.-H. Kuo, S.-J. Chang;, G.-Y. f, C.-P. Huang, G.-J. Ren, K.-T. Chiou, andC.-H. Ho, “A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirementon driving capability of reference voltage buffers,” IEEE Asian Solid-State CircuitsConference, pp. 293–296, 2013.
[6] T.-Y. Wang, M.-R. Lai, C. M. Twigg, and S.-Y. Peng, “A fully reconfigurable lownoisebiopotential sensing amplifier with 1.96 noise efficiency factor,” IEEE Transactionson Biomedical Circuits and Systems, vol. 8, no. 3, pp. 411 – 422, 2014.
[7] T.-Y. Wang, L.-H. Liu, and S.-Y. Peng, “Power-efficient highly linear reconfigurablebiopotential sensing amplifier using gate-balanced pseudoresistors,” IEEE Transactionson Circuits and Systems II: Analog and Digital Signal Processing, vol. 62,no. 2, pp. 199 – 203, 2015.
[8] S.-Y. Peng, L.-H. Liu, P.-K. Chang, T.-Y. Wang, and H.-Y. Li, “A power-efficientreconfigurable output-capacitor-less low-drop-out regulator for low-power analogsensing front-end,” IEEE Transactions on Circuits and Systems I: Fundamental Theoryand Applications, vol. 64, no. 6, pp. 1318 – 1327, 2017.
[9] S.-Y. Peng, Y.-H. Lee, T.-Y. Wang, H.-C. Huang, M.-R. Lai, C.-H. Lee, and L.-H.Liu, “A power-efficient reconfigurable OTA-C filter for low-frequency biomedicalapplications,” IEEE Transactions on Circuits and Systems I: Fundamental Theoryand Applications, vol. 99, no. 99, pp. 1 – 13, 2017.
[10] M. Yip and A. P. Chandrakasan, “A resolution-reconfigurable 5-to-10-bit 0.4-to-1V power scalable SAR ADC for sensor applications,” IEEE Journal of Solid–StateCircuits, vol. 48, no. 6, pp. 1453–1464, 2013.
[11] F. M. Yaul and A. P. Chandrakasan, “A 10 bit SAR ADC with data-dependent energyreduction using LSB-first successive approximation,” IEEE Journal of Solid–StateCircuits, vol. 49, no. 12, pp. 2825–2834, 2014.
[12] H. Tang, Z. C. Sun, K. W. R. Chew, and L. Siek, “A 1.33uW 8.02-ENOB 100 kS/s successive approximation ADC with supply reduction technique for implantableretinal prosthesis,” IEEE Transactions on Biomedical Circuits and Systems, vol. 8,no. 6, pp. 844–856, 2014.devices,” IEEE Transactions on Circuits and Systems I:Fundamental Theory and Applications, vol. 62, no. 9, pp. 2167–2176, 2015.
[15] Y. Tao and Y. Lian, “A 0.8-V, 1-MS/s, 10-bit SAR ADC for multi-channel neuralrecording,” IEEE Transactions on Circuits and Systems I: Fundamental Theory andApplications, vol. 62, no. 2, pp. 366–375, 2015.
[16] X. Zou, X. Xu, L. Yao, and Y. Lian, “A 1-V 450-nW fully integrated programmablebiomedical sensor interface chip,” IEEE Journal of Solid–State Circuits, vol. 44,no. 4, pp. 1067–1077, 2009.
[17] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in0.13-um CMOS for medical implant devices,” IEEE Journal of Solid–State Circuits,vol. 47, no. 7, pp. 1585–1593, 2012.
[18] H.-Y. Tai, Y.-S. Hu, H.-W. Chen, and H.-S. Chen, “A 0.85fJ/conversion-step 10b200kS/s subranging SAR ADC in 40nm CMOS,” IEEE International Solid-StateCircuits Conference, pp. 196–198, 2014.
[19] S. Liu, Y. Shen, and Z. Zhu, “A 12-bit 10 MS/s SAR ADC with high linearity andenergy-efficient switching,” IEEE Transactions on Circuits and Systems I: FundamentalTheory and Applications, vol. 63, no. 10, pp. 1616–1627, 2016.Transactions on Circuits and Systems I:Fundamental Theory and Applications, vol. 62, no. 10, pp. 2369–2379, 2015.
[22] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS,” IEEE Journalof Solid–State Circuits, vol. 47, no. 4, pp. 1022–1030, 2012.
[23] Z. Zhu, Z. Qiu, M. Liu, and R. Ding, “A 6-to-10-bit 0.5 V-to-0.9 V reconfigurable 2MS/s power scalable SAR ADC in 0.18um CMOS,” IEEE Transactions on Circuitsand Systems I: Fundamental Theory and Applications, vol. 62, no. 3, pp. 689–696,2015.
[24] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1- _w successiveapproximation ADC,” Proceedings of the Symposium on VLSI Circuits, pp. 236–237, 2009.
[25] C. C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mW 10-bit 50-Ms/s SARADC in 0.13um cmos process,” IEEE Journal of Solid–State Circuits, vol. 38, no. 7,pp. 1261–1265, 2003.
[26] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS withsplit capacitor array DAC,” IEEE Journal of Solid–State Circuits, vol. 42, no. 4,pp. 739–747, 2007.
[27] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mW 10-bit 50-MS/s SARADC in 0.13um CMOS process,” Proceedings of the Symposium on VLSI Circuits,pp. 236–237, 2009.
[28] Z. H. Cao, S. L. Yan, and Y. C. Li, “A 32mW 1.25GS/s 6b 2b/step SAR ADC in0.13um CMOS,” IEEE International Solid-State Circuits Conference, pp. 541–543,2008.
[29] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. Groot, “A 30fJ/conversion-step 8b0-to-10MS/s asynchronous SAR ADC in 90nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 388–390, 2010.
[30] P. Harpe, C. Zhou, Y.Bi, N. P. V. D. Meijs, X. Wang, K. Philips, G.Dolmans, andH. Groot, “A 26 uW 8 bit 10 MS/s asynchronous SAR ADC for low energy radios,”IEEE Journal of Solid–State Circuits, vol. 46, no. 7, pp. 1585–1595, 2011.
[31] S.-E. Hsieh and C.-C. Hsieh, “A 0.3-V 0.705-fJ/conversion-step 10-bit SAR ADCwith a shifted monotonic switching procedure in 90-nm CMOS,” IEEE Transactionson Circuits and Systems II: Analog and Digital Signal Processing, vol. 63, no. 12,pp. 1171–1175, 2016.
[32] Y. Zhang, E. Bonizzoni, and F. Maloberti, “A 10-b 200-kS/s 250-nA self-clockedcoarse-fine SAR ADC,” IEEE Transactions on Circuits and Systems II: Analog andDigital Signal Processing, vol. 63, no. 10, pp. 924–928, 2016.
[33] G. Geelen, “A 6 b 1.1 GSample/s CMOS A/D converter,” IEEE International Solid-State Circuits Conference, pp. 128–129, 2001.
[34] J. Jin, Y. Gao, and E. Sanchez-Sinencio, “An energy-efficient time-domain asynchronous2 b/step SAR ADC with a hybrid R-2R/C-3C DAC structure,” IEEE Journalof Solid–State Circuits, vol. 49, no. 6, pp. 1383–1396, 2014.
[35] H. Lee, S. Park, C. Lim, and C. Kim, “A 100-nW 9.1-ENOB 20-kS/s SAR ADC forportable pulse oximeter,” IEEE Transactions on Circuits and Systems II: Analog andDigital Signal Processing, vol. 62, no. 4, pp. 357–361, 2015.
[36] P. Harikumar, J. JacobWikner, and A. Alvandpour, “A 0.4-V subnanowatt 8-bit 1-kS/s SAR ADC in 65-nm CMOS for wireless sensor applications,” IEEE Transactionson Circuits and Systems II: Analog and Digital Signal Processing, vol. 63, no. 8,pp. 743–747, 2016.
[37] Y. Song, Z. Xue, Y. Xie, S. Fan, and L. Geng, “A 0.6-V 10-bit 200-kS/s fully differentialSAR ADC with incremental converting algorithm for energy efficient applications,”IEEE Transactions on Circuits and Systems I: Fundamental Theory andApplications, vol. 63, no. 4, pp. 449–458, 2016.
[38] C.-Y. Liou and C.-C. Hsieh, ““a 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SARADC with charge-average switching DAC in 90nm CMOS,” IEEE InternationalSolid-State Circuits Conference, pp. 280–281, 2013.
[39] Y.-J. Chen, K.-H. Chang, and C.-C. Hsieh, “A 2.02–5.16 fJ/conversion step 10 bithybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS,” IEEEJournal of Solid–State Circuits, vol. 51, no. 2, pp. 357–364, 2016.
[40] J.-Y. Lin and C.-C. Hsieh, “A 0.3 V 10-bit SAR ADC with first 2-bit guess in 90-nmCMOS,” IEEE Transactions on Circuits and Systems I: Fundamental Theory andApplications, vol. 64, pp. 562–572, 2017.