本論文為基於EPC UHF Gen2 Air Interface Protocol所設計之被動式RFID tag，應用在UHF頻帶中的925 MHz頻段。Tag包含射頻/類比前端電路、基頻處理器以及記憶體單元。
由於被動式RFID tag沒有外部電源供應，因此低功耗的設計格外重要，在射頻/類比前端電路以及基頻處理器的設計過程中，也都是以此為主要考量。
射頻/類比前端電路主要有四個功能，第一、轉換RF能量為直流電壓供電給整個電路。第二、偵測出輸入RF訊號中的訊息。第三、產生系統時脈以及重置訊號。第四、反射基頻處理器運算完的訊號回RFID interrogator。為了較低的功率消耗，我們以Beta-multiplier Voltage reference circuit取代Bandgap Voltage reference circuit，以Multivibrator取代其他功耗較高的震盪器。
基頻處理器則是處理收到的指令及參數後做出相對應的動作，例如改變標籤中flag的狀態、回傳random number或是讀取記憶體等等。而在降低功率消耗方面也運用了Clock gating、Operand isolation以及為編碼電路特別設計之演算法來達成。
記憶體單元在本論文中是以ROM實現，儲存了RFID tag的EPC、密碼以及使用者儲存的資料等等。其大小為64 words，每組word有16位元的資料。
晶片以TSMC 0.18 um CMOS process實現，考慮類比電路佈局後模擬以及數位電路APR後的功耗，於TT corner下晶片可工作之輸入功率範圍為-18.75至23 dBm。於量測時測得可工作之輸入功率範圍為-15至12 dBm，面積約為0.65 mm2。

In this work, we designe a low-power passive RFID tag based on EPC UHF Gen 2 Air Interface Protocol. The tag operates at 925 MHz and it comprises RF/analog frontend circuits, a baseband processor and memory unit.
Reducing power consumption is essential in passive RFID tags because they are not powered by any power supply. Consequently, the primary consideration for designing both analog and digital circuits is low power consumption.
The RF/analog frontend circuits have four functions. First, it converts the RF to DC to power the whole Tag. Second, it demodulates the input signal to data. Third, it generates the clock and the reset signals. Four, it backscatters data computed by the baseband processor to the interrogator. For less power consumption we employ the beta-multiplier voltage reference circuit instead of bandgap voltage reference circuit and use a multivibrator to generate the clock signal.
The baseband processor handles received commands and then operates accordingly, for instance, changing states of flags, replying random number, reading memory, etc. Also, in order to lower the power consumption, several low power techniques are employed, including clock gating, operand isolation and an algorithm developed for encoding.
The memory unit is a ROM in our design. It stores the Tag’s EPC, passwords and user data. It has 64 words and each word consists of 16 bits in the ROM.
The chip is designed and fabricated in TSMC 0.18 um CMOS process. Considering the power consumption of post-layout simulation for the analog circuits and simulation after APR for the digital circuits, the workable input power range is from -18.75 to 23 dBm at TT corner. The workable input power range is from -15 to 12 dBm in measuring. The chip area is approximately 0.65 mm2.

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