隨著超大型積體電路製程的進步，處理器與主記憶體之間的速度差距也不斷增加。為了縮短它們之間的差距，快取記憶體已成為不可或缺之橋樑，然而也增加可觀的功率消耗。在一般嵌入式系統中，快取記憶體的消耗功率佔了相當的比例。因此，如何降低快取記憶體的功率消耗已經成為嵌入式系統設計的重要議題之一。
在本論文中，我們藉由改良傳統快取記憶體架構的水平與垂直兩個層面，並觀察及分析處理器存取指令記憶體時的行為模式，提出一個低功率指令快取記憶體架構。在此架構中，我們綜合使用了三種技術，分別為區塊範圍偵測濾過式快取、資料記憶體槽化以及標籤記憶體存取忽略與資料記憶體致能控制。藉由這些技術，我們能有效地減少對第一層級快取的存取次數，並在存取第一層級快取時，可以盡可能減少對標籤記憶體與資料記憶體的存取次數，以降低功率消耗。
實驗結果顯示，相對於傳統四路集合關聯式快取記憶體，在不影響記憶體系統效能之下，減少了約55%的功率消耗。完成的低功率指令快取記憶體已經與Proto3-ARM9TM、AMBA匯流排與周邊智財整合，並分別在Xilinx Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.18 μm元件庫上實現。在FPGA實現部分，共消耗了10302個LUTs，最高操作頻率可達29 MHz。在元件庫實現方面，其所耗費的核心面積為 2.200 × 2.218 mm2，整體晶片面積為3.036 × 3.028 mm2，在129 MHz操作頻率下，平均功耗為147 mW。

The speed gap between processors and DRAM devices is increasingly widened along with the progress of integrated circuit technique. To bridge such a gap, the use of cache memory in between the processor and the main memory has become indispensable. Nevertheless, the addition of cache memory also consumes a lot of power, which is a large part of the total power dissipation of an embedded system. Consequently, the design of a low-power cache memory has become an important issue in an embedded system.
In this thesis, a low-power instruction cache architecture is proposed. This architecture is based on the improvement of conventional cache architecture from both horizontal and vertical aspects, as well as the access behavior of instruction cache memory. Based on this, three techniques, including the filter cache with block detection, the data memory sub-banking and tag check ignoring, and the enable control of data memory, are used. With these techniques, the power dissipation can be reduced by the reduction of the access of L1 cache and the access of the tag memory and data memory during accessing L1 cache.
The resulting architecture can reduce about 55% power consumption compared to the conventional 4-way set-associative instruction cache. In addition, the proposed instruction cache has been integrated with Proto3-ARM9TM, AMBA 2.0 system and related peripherals, designed previously in our lab, and implemented as well as verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library, respectively. When realized with the FPGA, the system consumes 10302 LUTs and operates at maximum frequently of 29 MHz. When realized with the cell library, the Proto3-ARM9TM has a core area of 2.200 × 2.218 mm2 and the whole chip area is 3.036 × 3.028 mm2. The average power consumption is 147 mW at the operating frequency of 129 MHz.

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