SiC MOSFET以其優越的性能和較低的損耗在大功率能量轉換領域獲得了廣泛關注和廣泛應用。在實際應用中，它們通常需要並聯連接，但不平衡的寄生參數會阻礙開關同步動作。因此，佈局中低且平衡的寄生電感至關重要。在本文中，我們提出了一種適用於並聯SiC器件的圓形佈局方案。並且這種對稱的圓形佈局設計，可以擴展以容納多個器件。
為了驗證所提出的圓形佈局方案的有效性，我們對電路電感進行了有限元分析模擬。 通過此分析，我們發現電路寄生電感與一般平列佈局方法相比顯著降低，並且在業界要求的範圍內。
通過實驗驗證，我們的研究論證了圓形佈局方案在並聯SiC器件中的可行性和有效性。該方案減少了電路寄生電感，同時提高了多個並聯器件切換的一致性。該研究為進一步優化SiC MOSFET的並聯佈局提供了有價值的見解。

SiC MOSFET have gained significant attention and widespread applications in the field of high-power energy conversion due to their superior performance and lower losses. In practical applications, they often require parallel connections, but unbalanced parasitic parameters can hinder synchronous switching. Therefore, low and symmetrical parasitic inductance in the layout is crucial. In this paper, we propose a circular layout scheme suitable for parallel SiC devices. This circular layout is symmetric and can be expanded to accommodate multiple devices.
To investigate the effectiveness of the proposed circular layout scheme, we conducted finite element analysis of the circuit inductance. Through this analysis, we found that the circuit inductance falls within a reasonable range and is significantly lower compared to conventional layout methods.
Through experimental verification, our research demonstrates the feasibility and effectiveness of the circular layout scheme in parallel SiC devices. The scheme reduces circuit parasitic inductance while maintaining consistency in the switching of multiple parallel devices. This research provides valuable insights for further optimizing the layout of SiC devices.

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