在本論文中，探討了一個十六位元殘值超取樣搭配二元視窗的十六位元逐次漸進式(successive-approximation register, SAR) 類比數位轉換器(analog-to-digital converter, ADC) 的設計與實現。由於對一個高解析度的類比數位轉換器來說，雜訊與線性度是晶片實現中最大的兩個挑戰。雜訊的部分主要是受到比較器的輸入相關雜訊所主導，因此在此設計當中，使用了低雜訊比較器來降低雜訊進而提升訊號雜訊比 (signal-to-noise ratio, SNR)。除此之外，還加入殘值超取樣 (residue oversampling, ROSR) 的技術，在會做四次的低位元殘值重覆取樣來做平均以得到更好的訊號雜訊比。在線性度方面，則是用了兩種方式來改善：一是二階電容交換技術 (Level-2 Capacitor Swapping) 以及快速二元視窗切換技術 (Fast Binary Window Switching)。二階電容交換技術的精隨在於將電容陣列以特殊的機制來進行交換，進而將電容的不匹配加以平均來得到更好的無雜散動態範圍 (spurious free dynamic range, SFDR)。而快速二元視窗切換技術是以減少不必要的電容切換以提升訊號對雜訊與失真比 (signal-to-noise-and-distortion ratio, SNDR)。
在台積電180奈米的 CMOS 製程下，本論文設計了一顆十六位元SAR ADC晶片。此晶片的操作電壓為3.3伏特以及1.8伏特，ADC消耗功率為1.6毫瓦，晶片總面積為1.95平方毫米。後模擬結果在取樣頻率為500 k Hz、輸入頻率為奈奎斯特頻率操作下，加入了ROSR技術可得到大約14.5 bits的有效位元數 (effective number of bits, ENOB)，SFDR約為100.68 dBc，性能指標 (Schreier Figure of Merit, FoMs) 約為168.58 dB。量測結果在取樣頻率為500 k Hz、輸入頻率為10kHz時，ENOB為11.75 bits，SFDR約為85 dBc，等效的性能指標約為155 dB。

This paper explores the design and implementation of a 16-bit Successive Approximation Register Analog to Digital Converter (SAR ADC) using a 16-bit residue oversampling (ROSR) combined with a binary window technique. In high-resolution ADCs, noise and linearity are the two major challenges in chip implementation. The noise component is mainly dominated by the input-related noise of the comparator. Therefore, in this design, low-noise comparators are used to reduce noise and improve the signal-to-noise ratio (SNR). Additionally, the residue oversampling (ROSR) technique is employed, which involves four consecutive samplings and conversions with averaging on the lower-weighted capacitors to achieve better performance.
Regarding linearity, two techniques are employed: Level-2 Cap Swapping and Fast Binary Window. The essence of Level-2 Cap Swapping is to switch the capacitors associated with the most significant bit (MSB) and the second-largest weight using a special switching mechanism. This averaging of capacitor mismatches helps to achieve a better spurious-free dynamic range (SFDR). On the other hand, Fast Binary Window uses the polarity of the first comparison result and combines it with subsequent comparison results to determine if the capacitor array needs to be switched, thus reducing unnecessary switching and improving the signal-to-noise and distortion ratio (SNDR).
In this paper, a SAR ADC chip is designed in a TSMC 180-nanometer CMOS process. The operating voltages of the chip are 3.3 volts and 1.8 volts, with a power consumption of 1.6 milliwatts for the ADC core. The total chip area is 1.95 square millimeters. The post-simulation results at a sampling frequency of 500 kHz and input frequency at the Nyquist frequency show that incorporating the ROSR functionality yields an effective number of bits (ENOB) of approximately 14.5 bits, SFDR of approximately 100.68 dBc, and a figure of merit (FoM) of approximately 168.58 B. The measurement results show that when the sampling frequency is 500 kHz and the input frequency is 10 kHz, the ENOB is 11.75 bits, the SFDR is about 85 dBc, and the equivalent performance index is about 155 dB.

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