本論文分別實現十位元、每秒一億萬次取樣之逐漸逼近式類比數位轉換器和十二位元、每秒一億萬次取樣之逐漸逼近式類比數位轉換器。使用二進位加權電容陣列來達到十二位元的精確度，並採用所提出之電容交換技術改善線性度和電容面積，取樣保持電路包含靴帶式電路及消除基體效應之控制開關以提升取樣開關線性度。使用N型輸入的動態比較器能有較佳的比較速度，非同步式控制邏輯可以避免需要使用到額外的高速外部時脈，並有效分配比較周期所需時間。

This thesis presents a 1.2-V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented and 1.2-V 12-bit 100MS/s successive approximation register analog-to-digital converter. By applying a Capacitor-Swapping Techniques that improve DAC linearity and reduce the area of DAC, so the proposed SAR ADC can achieve lower power consumption. In order to avoid using an external high frequency clock circuit to drive the ADC, asynchronous control logic is used A N-type dynamic latch comparator have high comparison speed. A bootstrapped switch with body effect reduction technique in the track-Hold circuit can further increase the sample linearity of the ADC.

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