微晶矽薄膜電晶體近來已被廣泛的研究，其擁有可大面積低溫成長的優點，且元件特性又優於非晶矽薄膜電晶體，例如，較高的電子移動率及較低的能帶間隙，普遍被認為將來可以取代非晶矽薄膜電晶體在大尺寸液晶顯示器上的應用地位。但微晶矽薄膜電晶體有一些先天上的問題，例如，漏電流過高、製程上的不均勻性，以及與多晶矽薄膜電晶體相比較差的元件特性等。為了增進微晶矽薄膜電晶體之元件特性，本論文將研究使用自我對準金屬矽化物製程設計微晶矽薄膜電晶體(Self-aligned silicided μC-Si TFTs scheme)以及上層閘極堆疊式微晶矽薄膜電晶體 (Top gate staggered-type μC-Si TFTs)的特性改良。
在本論文中，我們將經由模擬來探討微晶矽薄膜電晶體，一開始會先討論使用自我對準金屬矽化鎳設計的微晶矽薄膜電晶體。我們發現與上層閘極堆疊式薄膜電晶體比較，自我對準金屬矽化鎳設計的元件擁有較大的導通電流，這是因為在閘極施加偏壓時，源極端可以造成較大的能帶彎曲，使得較多的載子可以形成穿隧電流，同時源汲極電極較靠近通道其寄生串聯電阻較小。接著改變不同的金屬矽化物厚度，研究厚度對元件特性的影響。
接著我們研究對上層閘極堆疊式薄膜電晶體不同的通道層厚度對元件特性造成的影響，結果發現當通道層厚度與源汲極電極厚度相同時，其導通電流大於其他通道層厚度。最後與使用單一電極上層閘極堆疊式薄膜電晶體元件相比，使用堆疊電極可以達到較佳的nmos與pmos驅動電流。

Microcrystalline silicon thin-film-transistors (μC-Si TFTs) have been widely studied. Due to better device characteristic, and large area growth using a lower temperature process, compared to amorphous silicon thin-film-transistors, it has larger electron field mobility and lower energy band gap. Recently, it has been believed can substitute for the a-Si:H TFTs on large substrate area liquid crystal displays application status. However, μC-Si TFTs has some unavoidable problems, such as, large leakage current, non-uniform on fabrication, and worse device characteristic than polycrystalline silicon TFTs. For the improvement of device characteristic and the process simplification for μC-Si TFTs, in this thesis, μC-Si TFTs formed by using self-aligned silicided scheme and top gate staggered-type μC-Si TFTs structure have been studied, respectively.
In this thesis, μC-Si TFTs were examined by device simulation. First, the self aligned silicided scheme μC-Si TFTs are discussed. As compared to the previous top-gate staggered structure, the self-aligned silicided scheme leads to larger bending of energy band near the source region, which facilitates causing more carriers tunneling. In addition, for the top-gate staggered structure, since the source/drain electrode is spaced from the surface channel layer, the parasitic series resistance between the electrode and surface channel layer is considerably caused. As a result, the self-aligned silicided scheme can cause a larger conduction current than the top-gate staggered structure. Following, the silicide thickness of self aligned silicided scheme is changed, to study its influence to device characteristic.
Second, top gate staggered type μC-Si TFTs with difference channel layer thicknesses are discussed. It is found that, for a given electrode thickness, a proper channel layer thickness should be chosen to achieve better device characteristic. Finally, as compared with single electrode metal, the stacked electrode can achieve a better trade-off between nmos and pmos driving current.

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