Recent research in yield enhancement techniques and mitigation of device mismatch is presented. Systematic and random mismatch is studied and identified as the cause of device mismatch. Optimization of IC parameter yield is suggested and conducted with help of a new methodology based on mathematical programming. An algorithm for the optimal area allocation of critical matched devices is shown as well as algorithms for common centroid layout of different sized devices. Newly developed algorithms are presented on R-2R DAC as it is a common IC and comparison to other solutions is given.

Recent research in yield enhancement techniques and mitigation of device mismatch is presented. Systematic and random mismatch is studied and identified as the cause of device mismatch. Optimization of IC parameter yield is suggested and conducted with help of a new methodology based on mathematical programming. An algorithm for the optimal area allocation of critical matched devices is shown as well as algorithms for common centroid layout of different sized devices. Newly developed algorithms are presented on R-2R DAC as it is a common IC and comparison to other solutions is given.

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