隨著先進製程的發展，金屬氧化物半導體場效電晶體的電氣特性變化變得越來越受到佈局效應影響，像是氧化物擴散區距離以及氧化物和氧化物之間的距離效應。由於這些佈局效應，使得兩個擁有特定種類的單元以特定方向相鄰擺置時，會產生時序風險。
為了減輕主要路徑上的時序風險進而優化目標電路的性能，這篇論文將著重於利用單元翻轉和單元移動的多重行高細部擺置。我們首先設計了一個整數線性規劃公式，該公式可以解出有風險的相鄰單元組合以及單元位移的最佳解。之後，又提出了一個動態規劃的方法，該方法有更好的效率，並且也能夠得出接近最佳解的答案。 此外，整數線性規劃公式只能透過將電路劃分為子問題以得到在可接受的時間範圍內的解，和整數線性規劃不同的是，動態規劃的方法可以一次同時考慮整個電路的主要路徑上會產生風險的相鄰單元組合。實驗結果也證明了這篇論文提出的動態規劃方法具有其效率及有效性。

With the development of advanced process technology, the electrical characteristic variation of MOSFET transistors has been seriously influenced by layout dependent effect (LDEs), such as the length of oxide diffusion (LOD) and the oxide-to-oxide spacing effect (OSE). Due to these LDEs, two cells of specific cell types may suffer from timing degradation when they are adjacently and closely placed with specific orientations. To mitigate the timing risk of critical paths and thus optimize the performance of a target design, this work focuses on multi-row-height detailed placement with cell flipping and cell shifting. We first develop an integer linear programming (ILP) formulation that can optimally solve the problem in terms of risky cell abutments and cell displacements. After that, a dynamic programming (DP)-based method is proposed that is much more efficient and can also derive near-optimal solutions. In addition, in contrast with ILP that can only derive solutions within acceptable runtimes by partitioning a design into sub-problems, the DP-based method is able to simultaneously consider the risky abutments on the critical paths of the entire circuit at a time. Experimental results shows the efficiency and effectiveness of the proposed DP-based approach.

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