頻率合成器是用來做訊號頻率的升降之用，其必須滿足嚴格的要求，故它的設計乃是射頻系統中最具挑戰的一環。其中，壓控振盪器與除頻器更是頻率合成器電路裡的核心電路之ㄧ。對壓控振盪器而言，必須提供低相位雜訊的輸出，以避免相鄰雜訊訊號經由混波轉換產生干擾。而壓控振盪器的輸出會經由除頻器降頻至與參考訊號相同的等級，與相位頻率偵測器做比較以校正壓控振盪器的輸出，故除頻器需要有高頻操作的能力。由於應用於無線通訊系統中，壓控振盪器與除頻器都必須要有低功耗的特性。
本論文提出了兩個壓控振盪器與一個除頻器電路。其中壓控振盪器是使用兩組變容器串聯的BBS(back-back-series)架構振盪器。一個四相位雙頻壓控振盪器，雙頻帶具有很大的輸出振幅大小。以上電路使用台積電90奈米CMOS製程來完成。另一個使用鬆餅狀電晶體做注入混波的注入鎖定除頻器，使用0.35微米CMOS製程去實現。
首先，我們呈現一個使用鬆餅狀架構注入電晶體當混波的電路，與一般傳統電晶體不同的是新架構注入電晶體能有效降低汲/源集間的寄生效應，又因為藉由減少電晶體使用面積，所以能改善混波之後注入鎖定除頻電路使我們可以得到更佳的除二的功能。當供給電壓為0.9 V時，在注入強度為0dBm時，其除二模數的鎖頻範圍為4.25至6.35GHz。
其次，我們提出一個將p型交叉耦合對與n型Colpitts交叉對組成的LC振盪器、透過BBS變容器架構改善相位雜訊之壓控振盪器的技術。當控制電壓由0到1.15 V變化時，壓控振盪器的低頻帶可由6.11 GHz調到6.413 GHz，而高頻帶則由9.72 GHz到10.24 GHz。而在低頻帶輸出頻率6.4GHz，所量測到的相位雜訊在1 MHz位移時為-122.79 dBc/Hz。
最後，我們討論一個四相位雙頻壓控振盪器，其架構是由N型交叉耦合對的雙共振腔壓控振盪器，與利用P型上方堆疊環形機制產生四相位輸出。當供給電壓為1V，其功耗為4.85mW，壓控振盪器的低頻帶可由4.81 GHz調到5.6 GHz，而高頻帶則由9.67 GHz到10.33 GHz。而在高頻帶輸出頻率9.67GHz，所量測到的相位雜訊在1 MHz位移時為-114.84 dBc/Hz。

Frequency synthesizers are used to implement for the frequency up/down converting of signal. Because they have to meet a strict requirement, frequency synthesizers still be the most challenging part of RF system design. In a frequency synthesizer, voltage-controlled oscillator (VCO) and frequency divider are the key building blocks. For VCOs, low phase-noise outputs are required to avoid corrupting the mixer-converted signal by close interfering tones. The frequency of output signal of VCOs is divided down to the level of reference signal, and is compared with reference signal by a phase frequency detector (PFD) to adjust the outputs of VCOs. Therefore the frequency dividers must have the ability of high frequency operation. Because of wireless application, both of them should operate at low power consumption.
This thesis proposes two VCOs and one frequency divider. The VCO utilizes BBS (back-back-series) topology with two pairs of varactor in series. One is QVCO which output powers at both bands are large. The above circuits are fabricated in the TSMC 90 nm CMOS process. Another one is ILFD (Injection locked frequency divider) which applies waffle-like transistor as a mixer in the TSMC 0.35μ m CMOS process.
Firstly, we present an ILFD injection MOSFET which is based on a waffle-like transistor as a mixer. The difference between waffle-like transistor and the traditional one is the waffle-like topology can efficiently reduce parasitic effects of drain/source junction area. Because the new topology can also decrease the overall area of injection transistor, it can improve the divide function of ILFD after mixing the injection signal. At the supply voltage of 0.9 V, at the incident power of 0 dBm the locking range in the divide-by-2 mode is from the incident frequency 4.25 to 6.35 GHz.
Secondly, we propose a LC resonator with a p-type cross-coupled pair and an n-type Colpitts cross-coupled pair. Through BBS varator topology, it improves the phase noise of the VCO. The oscillating low-band frequency of the VCO can be tuned from 6.11 GHz to 6.413 GHz, and the oscillating high-band frequency of the VCO can be tuned from 9.72 GHz to 10.24GHz while the tuning voltage varies from 0 V to 1.15 V. The phase noise of the low band oscillation frequency 6.4 GHz is -122.79 dBc/Hz at 1 MHz frequency offset.
Finally, a dual-band quadrature voltage-controlled oscillator (QVCO) comprises two n-core cross-coupled dual-resonance VCOs and top-stacked pMOSFETs for quadrature phase generation. At the supply voltage of 1 V, the total power consumption is 4.85 mW. The free-running frequency of the QVCO is tunable from 9.67/4.81 GHz to 10.33/5.6 GHz as the tuning voltage is varied from 0.0/0.6 V to 0.55/1.2 V. The measured phase noise at 1MHz frequency offset is -114.84 dBc/Hz at the oscillation frequency of 9.67 GHz.

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