在RF射頻收發機中，PLL的特性非常重要，PLL內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而為了追求低功耗，低相位雜訊，與較寬的除頻範圍，在這其中又以壓控振盪器和注入鎖定除頻器特性最重要，而本論文主要研製鎖相迴路之注入鎖定除頻器。

首先，第一部分我們呈現一個寬頻除三注入鎖定除頻器，此除頻器使用台積電矽鍺0.18μm製程，晶片面積為0.859×0.817mm2。此除三除頻器設計基於一電容耦合的壓控振盪器，且利用電阻加入共振腔來增加除頻範圍。此除頻器最佳工作電壓操作在0.8伏特，整體功耗為5.26mW，在注入強度為0dbm時，除頻範圍可從6.2GHz~12.6GHz，百分比為68.09%。

接著，第二部份我們呈現一個寬頻除二注入鎖定除頻器，由台積電0.18μm製程實現。此除二除頻器使用電容交叉耦合nMOS對和雙並聯四階右手RLC共振腔。在工作偏壓0.75V、注入強度0dBm下，除二範圍總共為7.5GHz，注入頻率從3.6GHz~11.1GHz，總除頻百比例為102.04%。此除頻器功耗為4.875mW，晶片面積1.008×1.182mm2。

最後，第三部份我們呈現一個寬頻除四注入鎖定除頻器，同樣使用台積電0.18μm製程來實現。此除頻器使用電容交叉耦合nMOS對與雙並聯四階RLC所組成的六階RLC共振腔。在VT的調整下，可使高頻和中頻鎖住範圍重疊，形成一個較寬除頻範圍。在驅動偏壓為1.2V、注入功率為0dbm時，注入鎖定頻率為13~19GHz，鎖住範圍共6GHz，百分比為37.5%。此晶片面積為1.008×1.182mm2，除頻器的核心功耗共7.09mW。

In the RF transceiver, PLL are very important, PLL characteristics include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider. This thesis presents the design of Injection-Locked Frequency Dividers (ILFDs).

First, a wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The die area is 0.859 × 0.817 mm2. The ILFD circuit bases on capacitive cross-coupled oscillator and uses resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 5.26 mW and the locking range is from 6.2 to 12.6 GHz (68.09%) at injection power Pinj = 0 dBm.

Secondly, a wide locking range divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD uses a capacitive cross-coupled nMOS pair and two shunt 4th-order RLC resonators. At the drain-source bias of 0.75 V, and at the incident power of 0 dBm the maximum locking range of the divide-by-2 ILFD is 7.5 GHz (102.04%) from 3.6 to 11.1 GHz, the ILFD has overlapped locking ranges. The core power consumption is 4.875 mW. The die area is 1.008 × 1.182 mm2.

Finally, a wide locking range divide-by-4 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-4 ILFD uses a capacitive cross-coupled nMOS pair and two shunt 4th-order RLC resonators. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm, the locking range of the divide-by-4 ILFD is 6 GHz, from the incident frequency 13 to 19 GHz and the locking range percentage is 37.5%. The die area is 1.008 × 1.182 mm2. The power consumption of ILFD core is 7.09 mW.

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