研究生: |
黃冠傑 Guan-Jie Huang |
---|---|
論文名稱: |
超寬鎖頻範圍之除三注入鎖定除頻器與左手共振腔架構多頻帶壓控振盪器之設計 Design of Ultra Wide-Band Divide-by-3 Injection-Locked Frequency Divider and Multi-Band Oscillator Using Left-Handed Resonator |
指導教授: |
張勝良
Sheng-Lyang Jang 徐敬文 Ching-Wen Hsue |
口試委員: |
馮武雄
Wu-Shiung Feng 陳國龍 none |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2014 |
畢業學年度: | 102 |
語文別: | 英文 |
論文頁數: | 83 |
中文關鍵詞: | 壓控振盪器 、注入鎖定除頻器 |
外文關鍵詞: | voltage-controlled oscillator, injection-locked frequency divider |
相關次數: | 點閱:255 下載:0 |
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本論文提出三個電路,第一個電路先描述一個超寬鎖頻範圍除三注入鎖定
除頻器,是使用TSMC 0.18 μm CMOS 製程。此注入鎖定除頻器是使用雙諧振
LC 共振腔以及線性混波器來擴展鎖頻範圍。量測結果為供應電壓0.85 V,而高
頻和低頻分別在3.79 和2.37 GHz,核心功耗為7.39 mW。注入訊號為0 dBm 時,
其除三鎖頻範圍為6.1 至12.9 GHz (71.58%)。
第二個電路描述一個除三寬鎖頻範圍注入鎖定除頻器,此電路是使用TSMC
3P6M BiCMOS 0.18 μm 製程所實現,量測結果為供應電壓0.85 V,而可調範圍
則是使用電壓來改變可變電容,達到頻率可調的機制。可調範圍由3.4 GHz 至
3.853 GHz,當注入訊號功率為0 dBm 時,其總鎖頻範圍為10.1 GHz 至12.3 GHz
(19.64%),總功耗為8.56 mW。
最後一個電路是描述一個左手LC 網路架構的多頻帶壓控振盪器,是使用
TSMC 0.18 μm CMOS 製程,此電路以兩對交叉耦合器來補償左手共振腔的阻
抗,至於多頻帶的產生是先以電壓控制變容器來產生雙頻帶,再藉由電晶體切換
II
方式產生另外兩個頻帶。量測數據結果,輸出訊號分別為3.77 GHz、4.19 GHz、
5.03 GHz、5.9 GHz。
range. The
core power consumption of the ILFD core is 7.39 mW. The divider’s free-running
frequency has dual-bands at 3.79 and 2.37 GHz by switching the varactor’s control
bias, and at the incident power of 0 dBm the locking range is 6.8 GHz (71.58%), from
the incident frequency 6.1 to 12.9 GHz.
The second circuit is a wide locking range divide-by-3 injection-locked
frequency divider (ILFD) using a TSMC 0.18 μm SiGe 3P6M BiCMOS technology is
presented. The BiCMOS ILFD circuit is realized with a MOS divide-by-3 ILFD, with
two HBT pre-amplifiers used to amplify the input signal. The injection MOS can be
biased in sub or above-threshold region depending upon the output signal strength of
pre-amplifiers. The core power consumption of the ILFD core is 8.56 mW. The
divider’s free-running frequency is tunable from 3.4 to 3.853 GHz by tuning the
varactor’s control bias, and at the incident power of 0 dBm the maximum locking
range is 2.2 GHz (19.64%), from the incident frequency 10.1 to 12.3 GHz. The
operation range is 3.2 GHz (29.91%), from 9.1 to 12.3 GHz.
Finally, an oscillator with multi frequency band outputs. The proposed VCO has
been implemented with the TSMC 0.18μm 1P6M CMOS technology and the die area
of the oscillator is 0.43 × 0.82 mm2. The oscillator uses a CMOS cross-coupled VCO
as the core and a left-handed (LH) LC network so that the resonator has dual resonant
IV
frequencies. The oscillator can generate differential signals at the frequencies of 3.77
GHz, 4.19 GHz, 5.03 GHz, and 5.9GHz by using concurrent varactor and tail
switching.
[1] J. Roggers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House,
2003.
[2] B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
[3] B. Razavi, “A study of phase noise in CMOS oscillators, ” IEEE J. Solid-State
Circuits, vol. 31, p.p. 331-343 Mar. 1996.
[4] K. Shu, E. Sanchez-Sinencio, CMOS PLL Synthesizers : Analysis and Design,
Springer, 2005.
[5] A. Porret, T. Melly, C. Enz, and E, Vittoz, “Design of high-Q varactors for
low-power wireless applications using a standard CMOS process,” IEEE J.
Solid-State Circuits, vol. 35, pp. 337-345, Mar. 2000.
[6] F. Svelto, P. Erratico, S. Manzini, and R. Castello, “A metal oxide semiconductor
varactor,” IEEE Electron Device Lett., vol. 20, pp. 164-166, Apr. 1999.
[7] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,”
IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, Jun. 2000.
[8] T. Soorapanth, C. Yue, D. Shaeffer, T. Lee, and S. Wong, “Analysis and
optimization of accumulation-mode varactor for RF ICs,” in 1998 Symp. VLSI
Circuits Dig. Tech. Papers, , pp. 22-23. Jun. 1998.
[9] J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF
applications,” Kluwer Academic Publishers, 2004.
[10] J. Craninckx, and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800
frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp.
2054-2065, 1998.
[11] Y. K. Koutsoyannopoulos and Y. Papananos, “Systematic analysis and modeling
of integrated inductors and transformers in RF IC design,” IEEE Trans. Circuits
and System-II, vol. 47, no. 8, pp. 699-713, 2000.
[12] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in
CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628,
Apr. 2001.
[13] Y. Koutsoyannopoulos, “Novel Si integrated inductor and transformer structure
for RF IC design,” Proc. ISCAS , vol. 2, pp. 573-576, June. 1999.
[14] C. Tang, C. Wu, and S. Liu, “Miniature 3-D inductors in standard CMOS
80
process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, 2002
[15] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,”
IEEE Trans. on Parts, Hybrids and Packaging, vol. PHP-10, no.2, pp. 101-109,
1974.
[16] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J.
Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[17] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz
VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits
Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
[18] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
[19] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus
divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits,
vol. 31, pp. 890-897, July 1996.
[20] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31,
pp. 456-463, Mar. 1996.
[21] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS
technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[22] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency
dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[23] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider
up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits
Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[24] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25
um standard CMOS,” IEEE International Symposium on Circuit and System
(ISCAS), vol. 5, pp. 741-744, May 2000.
[25] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider
with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech.
Papers, pp. 412-413, Feb. 2001.
[26] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS
injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits,
pp. 47-50, June 2001.
[27] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking
Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol.
37, pp. 845-851, July 2002.
[28] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic
injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid
State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
81
[29] H. Wu, “Signal generation and processing in high-frequency/high-speed siliconbased
integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[30] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61,
pp.1380-1385, Oct. 1973.
[31] H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3
injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, Feb.
2006, pp.27–29.
[32] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang, “Divide-by-3 LC injection
locked frequency divider implemented with 3D inductors,” IEICE Trans.
Electron., vol. E91-C, no. 6, pp. 956–962, Jun. 2008.
[33] S.-L. Jang, C.-Y. Lin, and C.-F. Lee, “A low voltage 0.35 μm CMOS frequency
divider with the body injection technique,” IEEE Microw. Wireless Compon.
Lett., vol. 18, no. 7, pp.470–472, July 2008.
[34] S.-L. Jang, C.-C. Liu, and J.-F. Huang, ” Divide-by-3 injection-locked frequency
divider using two linear mixers,” IEICE Trans. on Electron.,
Vol.E93-C,No.1,pp.136-139, Jan. 2010.
[35] S.-L. Jang, and C.-W. Chang, ” A 90nm CMOS LC-tank divide-by-3
injection-locked frequency divider with record locking range,” IEEE Microw.
Wireless Compon. Lett., vol. 20, pp.229-231, April, 2010.
[36] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3
injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless
Compon. Lett., vol. 20, pp.390-392, July, 2010.
[37] S.-L. Jang, Y.-S. Chen, C.-W. Chang and C.-C. Liu,” injection-locked frequency
dividing apparatus”, US patent # US008305116B2, 2012.
[38] Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang,
“Low-voltage K-band divide-by-3 injection-locked frequency divider with
floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60,
no. 1, pp. 160–67, 2012.
[39] S.-L. Jang, and J.-Hs. Hsieh, ” A wide-locking range ÷3 injection-locked
frequency divider using concurrent injection mechanisms,” Analog Integr Circ
Sig Process, Vol. 77, Issue 3, pp 593-598., Dec. 2013.
[40] S.-L. Jang, C.-W. Tai, and C.-F. Lee, “Divide-by-3 injection locked frequency
divider implemented with active inductor,” Microw. Opt. Technol. Lett., vol. 50,
no. 6, pp. 1682–1685, June, 2008.
[41] S.-L. Jang and C.-Y. Chuang, ” Wide-locking range ÷3 series-tuned
injection-locked frequency divider,” Analog Integr Circ Sig Process, Vol. 76, 1,
pp. 111-116., Jan. 2013.
[42] C.-C. Liu, C.-C. Wang, S.-L. Jang, and M.-H. Juang,” A SiGe
82
injection-locked-oscillator using HBT injector operated in saturation region,”
Microwave Opt Tech Lett., pp.734-737, April, 2011.
[43] S.-L. Jang, C.-W. Chang, C.-L. Cheng, C.-W. Hsue, and C.-W. Hsu, " A
wide-locking range divide-by-3 LC-tank injection-locked frequency divider,” pp.
1-4, IEEE Int. VLSI- DAT, 2011.
[44] S.-L. Jang, C.-W. Hsu, C.-W. Chang and C.-W. Hsue, ” Wide-band 3 injection
locked frequency divider in 0.35 μm SiGe BiCMOS,” Microwave Opt Tech
Lett., pp.609-611, March, 2011.
[45] C.-C.Wang, Z. Chen, V. Jain, and P. Heydari, “Design and analysis of a
silicon-based millimeter-wave divide-by-3 injection-locked frequency divider,”
in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems, Jan. 2009.
[46] S.-L. Jang, C.-W. Huang, C.-W. Chang, and C.-W. Hsue, ” A parallel-injection
Injection locked frequency divider in 0.35 μm SiGe HBT process,” Microwave
Opt Tech Lett ., pp.379-383, Feb., 2012.
[47] S.-L. Jang, J.-F. Huang, C.-W. Huang C.-W. Hsue and C.-W. Chang, ”
Low-voltage wide-locking range LC-tank divide-by-3 injection-locked
frequency divider” Int. J. Electron. Letts. Vol. 1, pp.62-68, 2013.
[48] S.-L. Jang, R.-K. Yang, C.-C. Liu, and C.-W. Hsue, "A low power SiGe
BiCMOS series-tuned divide-by-3 injection locked oscillators," Microwave Opt
Tech Lett 51, 2239–2242, 2009.
[49] S.-L. Jang, Y.-H. Chuang, C.-C. Chen, J.-F. Lee, and S.-H. Lee, “A CMOS
dual-band voltage controlled oscillator,” in Proc. IEEE APCCAS, Dec. 2006, pp.
514–517
[50] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched
tuning,” in Proc. IEEE CICC, May 1998, pp. 555–558.
[51] S.-M. Yim and K. O. Kenneth, “Demonstration of a switched resonator concept
in a dual-band monolithic CMOS LC-tuned VCO,” in Proc. IEEE CICC, May
2001, pp. 205–208.
[52] S.-L. Jang, Y.-K. Wu, C.-C. Liu and J.-F. Huang, " A dual-band CMOS
voltage-controlled oscillator implemented with dual-resonance LC tank, " IEEE
Microw. Wireless Compon. Lett., vol. 19, pp.816-818, Dec. 2009.
[53] N. T. Tchamov, S. S. Broussev, I. S. Uzunov, and K. K. Rantala, “Dualband LC
VCO architecture with a fourth-order resonator,” IEEE Trans. Circuits Syst. II,
vol. 54, no. 3, pp. 277–281, Mar. 2007.
[54] S.-L. Jang, H.-H. Lin and C.-W. Hsue,” Mode-switching left-handed standing
wave voltage-controlled oscillator,” Microw. Opt. Technol. Lett. vol. 55, 9, pp.
1977–2244, Sept. 2013.
[55] S.-L. Jang, Y.-T. Chen, C.-W. Chang and M.-H. Juang, " Triple-band CMOS
83
voltage-controlled oscillator, " Microw. Opt. Technol. Lett., vol. 55, 4,
pp.737-740, Apr. 2013.
[56] S.-L. Jang, D.-A. Tu, C.-W. Chang and J.-F. Huang, "Dual-band CMOS
voltage-controlled oscillator with comparable outpower at both bands, "
Microw. Opt. Technol. Lett.,vol. 54, pp.2349-2352, Oct., 2012.
[57] S. Rong and H. C. Luong, "Analysis and design of transformer-based dual-band
VCO for software-defined radios," IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 59, no. 3, pp. 409–462, Mar. 2009.