本論文提出二個除頻器與三個壓控振盪器，第一個電路先描述一個使用線性混波器架構的除三注入鎖定除頻器，且使用 TSMC 0.35 μm CMOS 2P4M製程。此注入鎖定除頻器是由nMOS cross-coupled LC振盪器與二個注入MOSFETs串聯而成。量測結果為供應電壓1.2 V，而可調範圍3.73至3.92 GHz，核心功耗為6.9 mW。注入訊號為0 dBm時，其除二鎖頻範圍為10.99 GHz至11.68 GHz。
第二個電路描述一個低功耗寬鎖頻除三注入鎖定除頻器，此電路是使用TSMC 0.18 μm CMOS製程，此注入鎖定除頻器是使用push-push cross-coupled n-core MOS LC共振腔振盪器架構，而可調範圍則是使用電壓來改變可變電容，達到頻率可調的機制。可調範圍由4.50 GHz至5.15 GHz，當入射功率為0 dBm時，最大鎖頻範圍為14.9 GHz至16.3 GHz (9%)其總鎖頻範圍為13.7 GHz至16.3 GHz (17.3%)，總功耗為5.88 mW。
設計一個使用TSMC 0.18 μm CMOS製程的Colpitts差動壓控振盪器，其架構是由全部是nMOS LC共振腔 Colpitts 壓控振盪器組成；一個gate-connected LC共振腔與一個drain-connected LC共振腔。偏壓0.7 V時操作在4.51 GHz，頻帶在1Hz偏移頻率下的相位雜訊為-119.47 dBc/Hz。電路的功率消耗為3.34 mW，可調電壓由0 V至2 V，可調範圍從4.51 GHz至4.71 GHz約為0.2 GHz。
設計另外一個使用TSMC 0.18 μm CMOS製程的Colpitts差動壓控振盪器，其架構是由全部是nMOS LC串聯型式的共振腔 Colpitts 壓控振盪器組成；使用基底順向偏壓MOSFET與閘極電感提升技術。偏壓0.7V時操作在6.9 GHz，頻帶在1Hz偏移頻率下的相位雜訊為-117.46 dBc/Hz。FOM為-187.42 dBc/Hz。電路的功率消耗為4.4 mW，可調電壓由0 V至2 V，可調範圍從6.51 GHz至7.13 GHz約為0.62 GHz。
最後一個電路是描述一個新的全積體化CMOS Clapp 四相位壓控振盪器，由二個差動n-core Clapp壓控振盪器與四個耦合pMOSFETs組成，使用TSMC 0.18 μm CMOS製程。電源0.9 V時電路的功率消耗為12.2 mW，晶片面積為0.574 × 0.866 mm2。可調電壓由0 V至2 V，可調範圍從7.89 GHz至9.3 GHz。頻帶在1Hz偏移頻率下的相位雜訊為-119.47 dBc/Hz。FOM為-185.71 dBc/Hz。

This thesis presents two divide-by-3 frequency dividers and three VCOs. Firstly, the circuit is a divide-by-3 frequency divider employing the linear mixer topology, the divider was fabricated in the 0.35 μm CMOS 2P4M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled nMOSFETs. At the drain bias voltage of 1.2 V, the divider free-running frequency is tunable from 3.73 to 3.92 GHz, and at the incident power of 0 dBm the operational locking range is about 0.69 GHz, from the incident frequency 10.99 to 11.68 GHz. The core power consumption is 6.9 mW. The die area is 0.83 × 0.94 mm2.
The second circuit is a new low power wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The push-push ILFD circuit is realized with a push-push cross-coupled n-core MOS LC-tank oscillator. The core power consumption of the ILFD core is 5.88 mW. The divider’s free-running frequency is tunable from 4.50 GHz to 5.15 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 1.4 GHz (9.0%), from the incident frequency 14.9 GHz to 16.3 GHz. The operation range is 2.6 GHz (17.3%), from 13.7 GHz to 16.3 GHz.
A differential Colpitts voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology is an all nMOS LC-tank Colpitts VCO, which uses a composite LC resonator consisted of one gate-connected tunable LC resonator and one drain connected LC resonator. At the supply voltage of 0.7 V, the output phase noise of the VCO is -119.47 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.51 GHz, and the figure of merit is -187.31 dBc/Hz. The core power consumption is 3.34 mW. Tuning range is about 0.2 GHz, from 4.51 to 4.71 GHz, while the control voltage was tuned from 0 to 2 V.
The other one low voltage differential Colpitts voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology is an all nMOS LC-tank VCO using a series inductor-varactor configuration, it uses forward-biased body MOSFET and inductive gate boosting technique. At the supply voltage of 0.7 V, the output phase noise of the VCO is -117.46 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 6.9 GHz, and the figure of merit is -187.42 dBc/Hz. The core power consumption is 4.4 mW. Tuning range is 0.62 GHz, from 6.51 GHz to 7.13 GHz, while the control voltage was tuned from 0 V to 2 V.
Finally, a new fully integrated, CMOS Clapp quadrature voltage-controlled oscillator (QVCO) is presented. The QVCO is composed of two differential n-core Clapp VCOs coupled by 4 pMOSFETs and was implemented in the 0.18 μm CMOS technology with 0.9 V supply voltage. The die area is 0.574 × 0.866 mm2. At the supply voltage of 0.9 V, the total power consumption is 12.2 mW. The free-running frequency of the QVCO is tunable from 7.89 GHz to 9.3 GHz as the tuning voltage is varied from 0 V to 2 V. The measured phase noise at 1 MHz frequency offset is -118.65 dBc/Hz at the oscillation frequency of 7.89 GHz and the figure of merit (FOM) of the proposed QVCO is about -185.71 dBc/Hz.

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