由於近來物聯網的興起，使得很多產業都能用新的模式發展業務，並且開發出許多新穎的應用，而物聯網的特色就是輕小、省電以及低成本，因此我們使用基於IEEE 802.11a/g網路通訊協定與正交分頻多工調變(Orthogonal Frequency-Division Multiplexing, OFDM)系統的WARP V3 Reference Design來達成低頻寬和低載波頻率的通訊系統。
為了達成這個目的，前人整合了新的RF模組AD9361使其可以傳送與接收低載波頻率的訊號，但經過測試使用了新的RF模組的封包錯誤率提高了不少，追查原因後發現是因為新的RF模組會有較大的頻率偏移，進而發現WARP V3 Reference Design在標準中規範的最大頻率誤差40ppm(part per million)時封包無法順利解調。
本論文的目的是基於WARP V3 Reference Design來增加原本的設計中所沒有的同步演算法，並調整訊號頻寬來達成低速的區域網路。由於頻寬變窄而子載波數目不變的情況下，每個子載波之間的間隔也會變小，因此對於頻率誤差的影響會更為敏感，而原有的設計中也無法偵測到誤差40ppm時的頻率偏移，且也沒有針對取樣時間誤差進行補償，在封包長度較長的情況下，封包錯誤率會提高。因此本論文的內容主要是針對載波頻率誤差以及取樣時間誤差來設計同步電路並整合到WARP V3 Reference Design中，使整個通訊系統能夠在頻率誤差40ppm的環境下也能夠順利解調封包，最後將實作的硬體電路燒入FPGA板來測試實際傳輸時的錯誤率及吞吐量。

Many industries are using new model to develop business due to the Internet of Things (IoT) is expanding at a rapid rate. The feature of IoT is small, light, low power consumption and low cost, so we use WARP V3 Reference Design which based on the Standard of IEEE 802.11a/g and OFDM PHY’s transceiver to achieve narrow bandwidth and low carrier frequency.

In order to implement the transceiver for IoT, predecessor integrated the RF AD9361 into the system, but AD9361 has larger frequency offset which cause higher packet error rate (PER); and further, WARP V3 Reference Design cannot demodulation successfully at frequency offset up to 40 ppm.

The purpose of this thesis is to design synchronization algorithm which based on WARP V3 reference design, and implement the low-data-rate WLAN. To meet this goal, subcarrier spacing should be reduced, also the time to transmit and receive packet should be increased, which makes OFDM modulation more sensitive to carrier frequency offset and sample frequency offset. Therefore, the main goal of this thesis is to propose a new algorithm for frequency offset estimation. Finally, we use the FPGA board to verify our algorithm.

[1]何宗哲. 針對IEEE802.11a無線區域網路標準設計之正交多頻分工基頻處理器與同步電路. 國立中山大學. 2004
[2] AD9361_Reference_Manual_UG-570
[3]802.11 Reference Design for WARP v3
[4] TSX-3225_40M(OUTD-2B-0166_ADI)
[5]Tuning the AD9361/AD9364[Analog Devices Wiki]
[6] Ahmad R.S. Bahai, Burton R. Saltzberg, Mustafa Ergen. Multi-Carrier Digital Communications: Theory and Applications of OFDM. Spring Science & Business Media.2006.
[7]Zhuo Sun, Tao Peng and Wenbo Wang. A novel sampling synchronization scheme for OFDM-based system with unified reference clock. EURASIP Joumal on Wireless Communications and Networking. 2012.
[8]Synchronization and Channel Estimation in OFDM: Algorithms for Efficient Implementation of WLAN Systems.
[9]Lydi Smaini. RF Analog Impairments Modeling for Communication Systems Simulation: Application to OFDM-based Transceiver. John Wiley & Sons. 2012.
[10]Michael Rice.Digital Communications: A Discrete-Time Approach. Pearson Prentice Hall.2008.
[11] Communications System Toolbox Examples. Mathworks.
[12]俞壹馨. 適用於正交分頻多工技術為基礎之無線通訊系統的通道等化器設計. 國立交通大學. 2004
[13]Michael Speth. Optimum Receiver Design for Wireless Broad-Band Systems Using OFDM-Part I. IEEE TRANSACTIONS ON COMUNICATIONS. 1999.
[14]賴俊豪.正交分頻多工之天線模組設計.台灣科技大學.2016.
[15] Hyung-Jin Choi, Sang-Hyun Do, Dong-Kyu Kim, Myeong-Hwan Lee. Fine position of the FFT window in multicarrier receivers. Samsung Electronics Co., Ltd. 1998.
[16]周加慶, Sampling Frequency Detection and Compensation for DAB Receiver.國立台北科技大學.2008.
[17]Elliot Briggs, Brian Nutter, Dan McLane. Sample Clock Offset Detection and Correction in the LTE Downlink. Journal of Signal Processing Systems. 2012.
[18]Dah-Chung Chang. Effect and Compensation of Symbol Timing Offset in OFDM Systems With Channel Interpolation. IEEE. 2008.
[19]林運翔. 無線都會網路之下行取樣頻率同步設計(Design of Sampling Clock Synchronization for WMAN Downlink). 國立交通大學. 2010.