6.4 MSPS 9位元混合強健式MASH-21連續時間三角積分調變器｜國立臺灣科技大學博碩士論文系統

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研究生：	張榮展 Jung-Chan Chang
論文名稱：	6.4 MSPS 9位元混合強健式MASH-21連續時間三角積分調變器 6.4 MSPS 9-bit Hybrid Sturdy MASH-21 Continuous-Time Delta-Sigma Modulator
指導教授：	姚嘉瑜 Chia-Yu Yao
口試委員:	陳筱青 Hsiao-Chin Chen 彭盛裕 Sheng-Yu Peng
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	71
中文關鍵詞：	連續時間三角積分調變器、雜訊移頻
外文關鍵詞：	Excess Loop Delay, Continuous-Time DSM
相關次數：	點閱：178 下載：2
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隨著影視與音樂產業的發展，對於中高解低度的類比至數位轉換器的需求上升，而三角積分調變器將會是合適的選擇。
本設計設計一個應用於影音影片的三角積分調變器,離散時間三角積分調變器將受到取樣頻率的限制，因此本設計使用連續時間三角積分調變器來實現寬信號頻帶之應用。架構上以Sturdy-MASH為基礎進行改良來消除第一級量化器產生之量化雜訊，在系統中第二級積分器後加入了低通濾波器以及在第一級量化器後加入D flip-flop來解決excess loop delay的問題。
本篇設計所設計之晶片採用TSMC 90-nm CMOS製程。供應電壓為1.2V，晶片總功率消耗23.9 mW，總面積為2.069 * 1.425mm^2。系統頻寬為6.4MHz，取樣頻率為640 MHz，故超取樣率為50，SNDR達64.6 dB，解析度為10.43位元。

As the film and music industry develops, the demand for analog-to-digital converters (ADCs) with medium-to-high resolution has increased. Delta-sigma modulator (DSM) is a suitable choice.
This paper designs a DSM for video and audio applications. Since the discrete-time DSM is limited by the sampling frequency, a continuous-time DSM is used in this paper to achieve a wide signal bandwidth. The Sturdy-MASH structure is improved to achieve third-to-fourth-order noise shaping. A low-pass filter and a D flip-flop are also added to solve the problem of excess loop delay (ELD).
The designed chip in this paper uses TSMC 90-nm CMOS process with a supply voltage of 1.2V, a total power consumption of 23.9mW, and a total area of 2.069 * 1.425 mm^2. The system bandwidth is 6.4MHz, the sampling frequency is 640MHz, and the oversampling ratio is 50. The SNDR reaches 60.5dB, and the resolution is 9.76 bits.

封面                                                                   1
摘要                                                                   i
ABSTRACT                                                               ii
致謝                                                                   iii
CONTENTS                                                               iv
LIST of TABLES                                                         vii
LIST of FIGURES                                                        viii
Chapter 1                                                              1
Introduction                                                           1
1.1 Motivation                                                         1
1.2 Thesis Organization                                                2
Chapter 2                                                              3
Introduction of Delta-Sigma Modulator[2]                               3
2.1 Nyquist Sampling and Oversampling                                  3
2.2 Nyquist sampling theorem                                           4
2.3 Quantization Noise                                                 5
2.4 Oversampling                                                       7
2.5 Noise shaping                                                      9
2.6 First-Order Single Loop Delta-Sigma Modulator                      10
2.7 Second-Order and Higher-Order Single Loop Delta-Sigma Modulator    11
2.8 MASH Delta-Sigma Modulator                                         13
2.9 Sturdy MASH Delta-Sigma Modulator                                  15
Chapter 3                                                              17
System Architecture Analysis and Simulation                            17
3.1 Hybrid Sturdy MASH-21 Delta-Sigma Modulator                        17
3.1.1 Continuous-Time HSMASH-21 Delta-Sigma Modulator                  18
3.2 System Behavior Simulations                                        22
3.2.1 RC Integrator                                                    24
3.2.2 Excess Loop Delay                                                26
3.2.3 Integrator Noise Consideration                                   28
Chapter 4                                                              33
Chip Implementation and Discussion                                     33
4.1 FFMC-PZ Topology Op-amp                                            33
4.2 Comparator                                                         41
4.3 Clock Driver                                                       44
4.4 The HSMASH-21 Circuit                                              45
4.5 Pre-Simulations of the HSMASH-21 System                            55
4.6 Post-Simulations of the HSMASH-21 System                           58
4.7 Performance Comparison                                             63
4.8 Discussion                                                         65
4.8.1 Layout Optimization                                              65
4.8.2 Improving the SNR Performance                                    66
Chapter 5                                                              68
Conclusions and Future Works                                           68
5.1 Conclusions                                                        68
5.2 Future Works                                                       68
5.2.1 Calculation of Load Effect                                       68
5.2.2 Multi-bit Quantizer                                              69
References                                                             70


                                

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