三角積分調變器(Delta-Sigma Modulators)因擁有高解析度而廣為人知，常被應用於低速、高解析度的資料轉換應用中，本篇論文採用三角積分調變器實現在聲頻應用中的類比數位調變器。在本論文前段，會說明如何根據系統應用決定規格、接著建立系統模型、推導系統整體轉移函式，最後選取適合的子電路來完成系統。
本論文為使用一個三階三角積分調變器，改良Sturdy-MASH架構以消除第一級量化雜訊。並加入前饋路徑，消除訊號分量對第一級積分器的輸出影響，藉此來提升整體系統的解析度。
本論文提出應用於聲頻系統的三角積分類比至數位轉換器。使用TSMC 0.18μm製成、操作在1.8 V電壓、訊號頻寬為24 KHz、取樣頻率為4.608 MHz。晶片總功率消耗989 μW ，總面積為3.028×1.568 mm^2，訊號對雜訊及失真的比值(SNDR)為 89.91 dB，相當於 14.64位元。

Delta-Sigma Modulators (DSMs) are well-known for their capabilities of offering high resolution digital signals. It is usually used in low-speed, high-resolution data-conversion applications. This thesis employs the delta-sigma modulator to realize an analog to digital converter for audio applications.
This thesis explains how we determine the specifications according to the applications in the beginning. Then, it introduces the way of building the system model, including the derivation of the system transfer function and the selection of appropriate sub-circuits to complete the design. This work uses a two-stage third-order hybrid sturdy MASH delta-sigma modulator to eliminate the first-stage quantization noise. According to the analysis and design, the signal bandwidth is set to be 24 kHz and the sampling frequency is chosen to be 4.608 MHz. In addition, a feed-forward path is included to eliminate the signal component at the output of the first integrator, thereby reducing the distortion caused by the first op- amp and improving the SNDR.
This work employs TSMC 0.18μm CMOS process to fabricate the DSM chips. The total power consumption of the chip is 989 μW, and the total area is 3.028×1.568 mm^2. The achieved SNDR is 89.91 dB, which is equivalent to an ENOB of 14.64 bits.

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