本論文實現兩個十位元高速取樣之漸進式(SAR)類比數位轉換器(ADC)。利用單次二位元輔助之架構來減少轉換週期，進而提升類比數位轉換器的操作速度。動態閂鎖電路(Dynamic latch)減少了比較器輸出至數位類比轉換器(DAC)切換開關的延遲時間，可以減少所需的轉換時間。使用單次二位元輔助之架構可以減少電容線性度要求以及切換電容的能量損失。多個比較器產生的偏移量誤差可以藉由偏移電壓之校正能有效地改善類比數位轉換器的訊噪比。同時設計了滿足高速漸進式類比數位轉換器的參考電壓緩衝器。
第一個晶片在台積電40奈米，實現一個十位元每秒四億次取樣連續漸進式類比數位轉換器，在0.9伏特操作電壓及400-MS/s操作頻率下，消耗功率是1.84毫瓦，後模擬結果的動態效能為，訊噪失真比為57.8dB，無雜散動態範圍為74dB。另一個晶片在台積電90奈米，實現一個十位元每秒二億次取樣連續漸進式類比數位轉換器，在1伏特操作電壓及200-MS/s操作頻率下，消耗功率是2.8毫瓦，後模擬結果的動態效能為，訊噪失真比為55.5dB，無雜散動態範圍為74dB。

Two 10-bit high-speed successive approximation register (SAR) analog-to-digital converters (ADCs) was implemented in this thesis. By applying 2b/cycle-assisted architecture, it reduces number of conversion cycles and thus speeds up the ADC operation. The proposed dynamic latch circuit decreases the delay from the comparator output to the DAC switches. The 2b/cycle-assisted SAR architecture can improve the DAC linearity and reduce the switching energy. The offset calibration scheme is proposed to effectively improve the SNR. The reference buffer is proposed to meet the high-speed SAR ADCoperation.
The first 10-bit ADC chip was implemented in TSMC 40nm CMOS. At 400-MS/s, It consumes a total power of 1.84 mW from a 0.9-V supply. bits. At Nyquist, the post-layout simulated SNDR and SFDR are 57.8 dB and 74 dB, respectively. The second 10-bit ADC chip was implemented in TSMC 90nm CMOS. At 200-MS/s, it consumes a total power of 2.84 mW from a 1V supply. bits. At Nyquist, the post-layout simulated SNDR and SFDR are 55.5 dB and 74 dB, respectively.

http://web.stanford.edu/~murmann/adcsurvey.html.
[2] Y.-Z. Lin et al, “A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS,” IEEE Transactions on Circuits and Systems, vol.60 , no. 3, pp.570–581 Feb. 20134.
[3] Y.-H. Chung et al, “A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS,” IEEE Trans. on VLSI Systems, vol.23 , no. 3, pp.557–566.
[4] W.-H Tseng et al, “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,” IEEE Journal of Solid-State Circuits, vol. 51, no. 10 , Oct. 2016.
[5] Y.-H. Chung et al, “A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 8, pp.999-1003, Aug.2018.
[6] Y.-H. Chung et al, “A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS,” in Proc. of International Symposium on Next Generation Electronics (ISNE), May 2018.
[7] S. Lee et al, “A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) , March 2014.
[8] C.-H. Chan et al, “A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMO,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) , March 2015.
[9] S.-W. Chen et al, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12 , Nov. 206.
[10] B. Wicht et al, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp.1148-1158, July 2004.
[11] C.-C. Liu et al, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits , vol. 45, no. 4, pp.731-740, March 2010 .
[12] C.-C. Liu et al, “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” IEEE International Solid-State Circuits Conference - (ISSCC),March 2010 .
[13] H.-K. Hong et al, “A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC,” IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 543-555, Nov, 2015
[14] P.M. Figueiredo, “Kickback noise reduction techniques for CMOS latched comparators,” IEEE Transactions on Circuits and Systems II, vol. 53, no. 7, pp. 541-545, July 2006.
[15] M. Dessouky and A. Kaiser “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” IEEE Electronics Letters, vol. 35, pp. 8-10, Jan. 1999.
[16] Y.-S. Hu, C.-H. Shih, H.-T. Tai, H.-W. Chen, H.-S. Chen, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40-nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2014, pp. 81.
[17] B.P. Ginsburg, and A.P. Chandrakasan, “500-MS/s 5-bit ADC in 65nm CMOS with split capacitor array,” IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.
[18] Y-H. Chung, M. Wu, and H. Li, “A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching,” IEEE Custom Integr. Circuits Conf. Sept. 2013
[19] C.-k. Lee, et al, “A replica-driving technique for high performance SC circuits and pipelined ADC design,” IEEE Trans. Circuits Syst. II, vol. 60, no. 9, pp. 557–561, Sep. 2013.
[20] C.-H.Chan et al, “60-dB SNDR 100MS/s-SAR ADC with Threshold Reconfigurable Reference error Calibration,” IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2576-2588 Oct.2017.
[21] J. Song, et al, “A 10-b 2b/cycle 300MS/s SAR ADC with a Single Differential DAC in 40nm CMOS,” in IEEE CICC, 2017, pp. 1-4.
[22] B.-S. Sung, et al, “A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2015, pp. 464-465.
[23] Y.-C. Lien, “A 14.6mW 12b 800MS/s 4x Time-Interleaved Pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration,” in IEEE Symposium on VLSI Circuits, Jun. 2016, pp. 1-2.
[24] K.-J. Moon, et al, “A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s Single-Channel Pipelined SAR ADC with a Current-Mode Fine ADC in 28nm CMOS,” in IEEE Symposium on VLSI Circuits, Jun. 2017, pp. 94-95.
[25] C.-C. Liu et al, “A 10-bit 320-MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20-nm CMOS,” in Proc. IEEE A-SSCC, pp. 77-80, 2014.
[26] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-mm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176–177.
[27] H. Wei et al, "An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC," IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2763–2772, Nov. 2012.
[28] J.Jin et al, "An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure," IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1383–1397, June. 2014.
[29] C-Ch Liu et al, “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process,” in IEEE Symposium on VLSI Circuits, Jun. 2009, pp. 236-237
[30] G. Y. Huang, S. J. Chang, Y. Z. Lin, C. C. Liu, and C. P. Huang, “A 10b 200MS/s 0.82mW SAR ADC in 40nm,” in Proc. IEEE A-SSCC, pp. 289-292, 2013.
[31] J.-H. Tsai et al, “A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS with digital error correction and correlated-reversed switching,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1382–1398, Jun. 2015.
[32] Y. Zhu, C.-H. Chan, S.-W. Sin, U. Seng-Pan, and R. Martins, “A 34fJ 10b 500MS/s partial-interleaving pipelined SAR ADC,” in IEEE symp. VLSI