第五代通訊技術(5G)的時代來臨，使得對網路的依賴日益漸增。其中5G最主要的目標在於高資料傳輸吞吐量、更低的延遲和節省能源以降低成本。在使用頻段方面，5G 新無線電(5G NR)提出的通訊標準大致可以6GHz以及30GHz作為一個界線，包括低於6GHz的低頻(FR1，Frequency Range 1)，以及大於6GHz與小於30GHz之頻段 (FR2)甚至大於30GHz更高頻的毫米波(mmWave)範圍。基於上述三個頻段5G有兩大關鍵新技術應用於此。第一為基於毫米波所需要的混合類比及數位的預編碼器，以減少基於波束成型的大規模MIMO收發器中的射頻元件和數據轉換器的數量。然而，傳統的混合預編碼技術無法配置為支持不同的系統規範，例如數據流或傳輸/接收天線的數量，而極大的限制了混合預編碼器的適用性和效率，並導致資源浪費。其次，在調變技術方面，在FR1與FR2頻段上基於傳統的正交分頻多工技術(OFDM)雖然有許多優勢，但是5G的各種目標對無線通訊系統的需求更高，因此在學術界以及產業界提出了濾波後正交分頻多工(Filtered-Orthogonal Frequency Division Multiplexing ; Filtered-OFDM)以作為5G調變候選的技術之一。Filtered-OFDM技術由於將整個頻帶被分成多個子帶，每個子帶分別承載單獨的數據訊息，其每一個子帶之單獨濾波能夠減少頻帶外發射(Out-of-Band Emission)，以及減少相鄰通道干擾（ACI，Adjacent-channel interference），因此具有在5G系統中達到預定效能的優勢。本論文基於混合預編碼技術與濾波後正交分頻多工技術(Filtered-OFDM)進行電路架構之最佳化設計。首先我們對於應用於毫米波的可調式混合預編碼器進行電路架構優化。我們改進混合預編碼器中之電路運作時序以達到共用電路元件，並因此而降低電路複雜度的目的。同時，我們的電路為基於迭代遞迴式架構以達到利用不同次數的運作迭代以支援可變的數據流或傳輸/接收天線的數量比的目的。另一方面，我們基於FR1以及FR2之Filtered-OFDM接收器進行電路架構優化與設計。具體而言，我們重新審視Filtered-OFDM接收器中之傳輸架構(FFT configuration)並重新設計FFT電路所需實現的系統規格，使其以最低的複雜度支援最多可能的5G應用規範。另外，我們針對濾波器組系統進行電路架構的最佳化，以達到減少運算元件並降低系統複雜度的目的。我們的混合預編碼器電路與Filtered-OFDM接收器電路皆以TSMC 40nm製程進行電路合成。依實驗證明，在工作頻率300MHz下，我們的混和預編碼氣電路使用了約263.5K個邏輯閘，數據傳輸吞吐量為11.1M 通道矩陣/s。與先前的預編碼文獻相比，我們的設計可以減少約30%的面積以及提升17.5%的硬體效率值。另一方面，在工作頻率200 MHz下，我們的Filtered-OFDM接收器使用了約14.75 M個邏輯閘。與先前的Filtered-OFDM文獻相比，我們的設計可以減少約45.6%的面積。綜合上述，本文提出了低硬體複雜度，且高數據吞吐量的可調式混合預編碼電路以及Filtered-OFDM接收器電路。

關鍵字 —第五代通訊技術，正交分頻多工，濾波後正交分頻多工，快速傅立葉轉換，波束成形技術，毫米波多輸入多輸出無線通訊系統，可調式，混合類比以及數位的預編碼技術

Due to the increasing dependence on the Internet, the era of the fifth generation of communication technology (5G) is coming. The main goal of the 5G communication is to achieve the 5G diverse scenario which has different standard requirements such as latency, data throughput, the transmission power, and many other indices in different service. In terms of using frequency bands, the communication standards proposed by the 5G New Radio (5G NR) can generally use 6GHz and 30GHz as a boundary, including frequency bands below 6GHz (FR1, Frequency Range 1), and frequency bands above 6GHz and less than 30GHz (FR2), and even higher than 30GHz which is also called millimeter wave (mmWave). As mentioned above three frequency range, there are two key technologies applied them in 5G communication. The first one is hybrid analog and digital precoding techniques which reduce the number of RF chains and data converter in mmWave MIMO system. However, traditional hybrid precoding techniques cannot be configured to support different system specifications, such as the number of data streams or transmit/receive antennas. The second key technology is regarding the modulation technology which Orthogonal Frequency Division Multiplexing (OFDM) has been widely used in wireless communication systems. Although the traditional OFDM has many advantages, the various targets of 5G have a higher demand for wireless communication systems. Therefore, filtered-OFDM has been proposed as one of the candidate technologies for 5G modulation scheme. Since in the filtered-OFDM the transmission band is divided into multiple subbands and each subband carries an independent data information, each subband filtering method can reduce out-of-band emission (Out-of-Band Emission) and adjacent channel interference (ACI). This thesis presents the optimization of the architecture for the configurable and efficient hybrid precoding processor in bit-stream-based mmWave MIMO systems as well as the optimization of the architecture for the configurable and low-complexity Filtered-OFDM baseband processor based on FR1 and FR2 band. Specifically, the proposed hybrid precoding processor is configurable to support one to four data streams with 16×16 millimeter-Wave MIMO systems. We optimized the data flow so as to enhance the efficiency for the utilization of the hardware component. The improved data flow results in a timing sharing scheme for employing the multipliers so that the hardware complexity can be reduced. Moreover, we design a novel iterative and pipeline architecture precoding processor which can configure the number of data stream to the number of RF chain ratio. Furthermore, we consider the Fast Fourier Transform (FFT) size and the filter size are the key parameter to have impact in the performance and the complexity of the filtered-OFDM receiver. Summarized the above two topics, the proposed hybrid precoding processor circuit is synthesized and been Automatic Placement/Routing (APR) with TSMC 40nm technology. The experiments show that the hardware complexity of our design is 263.5 KGEs and the data transmit throughput is 11.1 M channel-matrices per second with the 300 MHz clock speed. Compare to the state-of-art design, the proposed hybrid precoding processor reduces the hardware area by at least 30% and increases hardware efficiency by at least 17.5%. In addition, it is noted that the proposed architecture is the only one that supports configuration for different numbers of RF chains to transmission antennas ratios. Moreover, the proposed Filtered-OFDM baseband design and implemented circuit is synthesized with TSMC 40nm technology. Because of considering FFT sizes, and filter sizes, the experiments show that the hardware complexity of our design is 14.75 MGEs. Compare to the state-of-art, the proposed Filtered-OFDM reduces the hardware area by at least 45.6%.
Index Terms — Filtered-OFDM, FFT sizes, hybrid precoding processor, low complexity, configurable, hardware efficiency

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