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研究生: 呂毓駿
Yu-Jyun Lyu
論文名稱: 適用於ECG量測系統之連續漸進式類比數位轉換器設計
Design of Successive Approximation Analog-to-Digital Converter for an ECG Measurement System
指導教授: 陳筱青
Hsiao-Chin Chen
口試委員: 邱弘緯
Hung-Wei Chiu
姚嘉瑜
Chia-Yu Yao
郭重顯
Chung-Hsien Kuo
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 69
中文關鍵詞: 心電圖連續漸進暫存器類比數位轉換器時域比較器
外文關鍵詞: electrocardiograph (ECG), successive approximation register analog-to-digi, time-domain comparator.
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  • 在本論文中使用了TSMC 0.18μm CMOS製程,設計並實作兩個不同架構之適用於心電圖(electrocardiograph, ECG)量測系統的12-bit連續漸進式類比數位轉換器(Successive Approximation Analog-to-Digital Converter, SAR-ADC)。第一個為單端輸入的連續漸進式類比數位轉換器設計,電路中使用取樣保持電路(Sample-and-Hold circuit, S/H)、電容式數位類比轉換器(Capacitive Digital-to-Analog Converter, CDAC)、電壓比較器(Voltage Comparator)及連續漸進暫存器(Successive Approximation Register, SAR)電路所構成。在電路操作電壓為1.2 V,以及50 k-samples/s的取樣頻率下,具有55.33 dB的訊號對雜訊與失真比,相當於8.90 bits的有效位元數,消耗功率為12 µW。
    第二個為差動輸入的連續漸進式類比數位轉換器設計,電路中同樣使用了電容式數位類比轉換器與連續漸進暫存器,而比較器部份則使用時域比較器(Time-Domain Comparator)將數位類比轉換器所產生的電位差轉化為時間差進行比較,並以數位化的動態電流消耗取代了原先固定的靜態電流消耗。當電路操作電壓為1.2伏特,及50 k-samples/s的取樣頻率下,具有56.72 dB的訊號對雜訊與失真比,對應到有效位元數為9.13 bits,消耗功率為17.28 µW。
    最後使用本論文第二章中所實現的單端輸入類比數位轉換器,架構出了一個基本的心電圖量測系統。最後在論文中對多種心臟疾病描述其在心電圖波形上所產生的變化,以Fluke MPS-450模擬其波形並使用此量測系統進行量測。


    In this thesis, two implementations of Successive Approximation Register Analog-to-Digital Converters (SAR-ADCs) using TSMC 0.18μm CMOS process are presented. These SAR-ADCs are designed for electrocardiogram (ECG) measurement systems.
    The first ADC is a single-end-input SAR-ADC. A sample-and-hold circuit(S/H), a capacitive digital-to-analog converter (CDAC), a voltage comparator, and a successive approximation register (SAR) are used in this ADC. At a sampling rate of 50 k-samples/s, this ADC achieves a SNDR of 55.33 dB, equals to an ENOB of 8.88 bits. It consumes 12 µW with a supply voltage of 1.2 V.
    The second ADC is a differential input SAR-ADC. A time-domain comparator is used instead of a voltage comparator in this ADC. The voltage difference comes into time difference in time-domain comparator. At a sampling rate of 50 k-samples/s, this ADC achieves a SNDR of 56.72 dB, equals to an ENOB of 9.13 bits. It dissipates 17.28 µW from a supply voltage of 1.2 V.
    Finally, an ECG measurement system is implemented using the single-ended input SAR-ADC, which is presented in chapter 2. The system is used to capture the ECG signals from human body. And then, using Fluke MPS-450 to simulate how the disease affects the ECG waves and recording the influence by this measurement system.

    摘要 I Abstract III 誌謝 V 目錄 VI 圖目錄 IX 表目錄 XIII 第一章 緒論 1 1.1簡介 1 1.2章節概述 3 第二章 單端輸入類比數位轉換器 5 2.1簡介 5 2.2電路原理及架構 6 2.1.1取樣保持電路 6 2.1.2電容式數位類比轉換器 9 2.1.3電壓比較器 11 2.1.4連續漸進暫存器 11 2.3模擬結果 12 2.3.1取樣保持電路模擬結果 12 2.3.2電容式數位類比轉換器模擬結果 13 2.3.3電壓比較器模擬結果 15 2.3.4連續漸進暫存器模擬結果 15 2.3.5整體效能模擬結果 16 2.4量測結果與討論 18 2.4.1量測環境設定 18 2.4.2量測結果 21 2.4.3討論 24 2.5結論與比較 28 第三章 差動輸入電壓轉時域類比數位轉換器 30 3.1簡介 30 3.2電路原理及架構 31 3.2.1電容式數位類比轉換器 31 3.2.2電壓轉時域比較器 33 3.2.3連續漸進暫存器 34 3.3模擬結果 36 3.3.1電容式數位類比轉換器模擬結果 36 3.3.2電壓比較器模擬結果 36 3.3.3連續漸進暫存器模擬結果 37 3.3.4整體效能模擬結果 37 3.4量測結果與討論 38 3.4.1量測環境設定 38 3.4.2量測結果 41 3.5結論與比較 44 第四章 心電圖量測系統 45 4.1心電圖概述 45 4.2心電圖量測系統 47 4.2.1量測系統架構 47 4.2.2量測結果 49 4.3心電圖形判讀 52 4.4討論 58 4.5文獻比較 59 第五章 總結 61 參考文獻 63 作者簡介 69

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