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研究生: 黃耀宏
Yao-Hung Huang
論文名稱: 考量MLC STT-RAM讀/寫干擾之末級快取設計
Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 劉一宇
Yi-Yu Liu
吳晉賢
Chin-Hsien Wu
陳雅淑
Ya-Shu Chen
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 69
中文關鍵詞: 自旋記憶體快取記憶體寫入干擾讀取干擾
外文關鍵詞: MLC STT-RAM, Last level cache, Write disturbance, Read disturbance
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1 Introduction 2 Background 2.1 Single-Level-Cell (SLC) STT-RAM 2.2 Multi-Level-Cell (MLC) STT-RAM 2.3 Cache Mapping Strategy 2.4 Cache Hierarchy Management Policy 3 The problems of MLC STT-RAM 3.1 Write Disturbance in MLC STT-RAM 3.2 Read Disturbance in MLC STT-RAM 4 Read/Write Disturbance-Aware Design 4.1 System Architecture 4.2 Write Strategy for MLC STT-RAM Cache 4.3 Read Strategy for MLC STT-RAM Cache 4.4 Priority-based Victim Selection Policy 4.5 Swapping Mechanism 4.5.1 Migration Policy 4.5.2 Time Overhead of the Swapping Mechanism 5 Performance Evaluation 5.1 Experiment Setup 5.2 The Impacts of Di erent Settings for Th 5.3 The Comparison of Energy Consumptions 5.4 The Comparison of Access Latencies 5.5 The Comparison of Cache Miss Rate 5.6 The E ect of the Swapping Mechanism 6 Related Work 7 Conclusion A Other Comparison Figures

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