研究生: |
黃耀宏 Yao-Hung Huang |
---|---|
論文名稱: |
考量MLC STT-RAM讀/寫干擾之末級快取設計 Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache |
指導教授: |
謝仁偉
Jen-Wei Hsieh |
口試委員: |
劉一宇
Yi-Yu Liu 吳晉賢 Chin-Hsien Wu 陳雅淑 Ya-Shu Chen |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 資訊工程系 Department of Computer Science and Information Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 英文 |
論文頁數: | 69 |
中文關鍵詞: | 自旋記憶體 、快取記憶體 、寫入干擾 、讀取干擾 |
外文關鍵詞: | MLC STT-RAM, Last level cache, Write disturbance, Read disturbance |
相關次數: | 點閱:193 下載:0 |
分享至: |
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