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研究生: 鄭評
Ping Cheng
論文名稱: 透過提早寫回和置換減少MLC STT-RAM末級快取讀寫干擾之設計
Design of MLC STT-RAM-based Last Level Cache to Reduce Read/Write Disturbances by Early Eviction and Swapping
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 吳晉賢
Chin-Hsien Wu
黃元欣
Yuan-Shin Hwang
陳雅淑
Ya-Shu Chen
謝仁偉
Jen-Wei Hsieh
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 49
中文關鍵詞: 磁阻式隨機存取記憶體讀取干擾寫入干擾
外文關鍵詞: Spin Torque Transfer Random Access Memory, Swapping, Read Disturbance, Non-Volatile Memory
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  • 1 Introduction 2 Background 2.1 Basic Concept of STT-RAM 2.2 Multi-Level Cell (MLC) STT-RAM 2.3 Mapping Mechanisms 2.3.1 Direct Mapping 2.3.2 Interleaved Mapping 2.3.3 Cell Split Mapping 3 Early Eviction and Swapping 3.1 System Architecture 3.2 Early Eviction 3.3 Inter-cell Swapping 3.4 Analysis of Swapping Overhead 3.5 Threshold and Counter Overhead 4 Performance Evaluation 4.1 Experiment Setup 4.2 Comparison of Energy Consumption 4.3 Comparison of Access Latency 4.4 Comparison of Hard-way and Soft-way Accesses 4.5 Comparison of Miss Rates 4.6 Statistic of Swapping and Early Eviction 5 Conclusion

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