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研究生： 翁嘉奇
Jia-Chi Weng
論文名稱： 寬鎖頻範圍注入鎖定除二除頻器以及多共振注入鎖定除三除頻器
Wide-Locking Range Divide-by-2 Injection-Locked Frequency Dividers and Multi-Resonance 3:1 Injection Lock Frequency Dividers
指導教授： 莊敏宏
Miin-Horng Juang
張勝良
Sheng-Lyang Jang
口試委員: 徐世祥
Shih-Hsiang Hsu
王煥宗
Huan-Chun Wang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2018
畢業學年度： 106
語文別： 中文
論文頁數： 138
中文關鍵詞： 注入式 、除頻器 、除二 、多共振
外文關鍵詞： injection lock, Multi-Resonance, Divide-by-2 Injection-Locked
相關次數： 點閱：324  下載：19 
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  •  上一筆

    • 此論文提出四個電路，第一個是使用多路徑電感的除二除頻器，第二個是LC互感耦合除二除頻器，第三個是使用無變容器即能改變頻率與除頻範圍的除二除頻器，第三個是多共振腔3:1除三除頻器，第四個是四者皆使用了標準台積電0.18微米製程實現。
    第四章節描述第一個電路為一注入鎖定除頻器為除二電路，在此研究螺旋電感並存著寄生電容，因此每一個電感有獨立的LC振盪頻率。此電路架構有著三組電感組成，故能在沒有可變電容切換下得到多頻帶的除頻範圍。在此電路架構下我們設計使用兩種不同的電感去實現，第一種晶片使用台積電0.18微米製程，晶片面積大小為0.688×1.008 mm2。
    第五章節描述第二個電路是描述一個使用數位開關改變除頻範圍的除二注入鎖定除頻器，此電路使用台積電0.18微米製程。此注入式鎖定除二除頻器除頻範圍有兩個未重疊的頻帶，使用三組變容器與互感上的副電感並連，藉由數位調控變容器，其除頻範圍也跟著被改變。此晶片面積相當小，僅0.688×1.008 mm2。
    第六章節描述第三個電路呈現一個無需變容器即能調變除頻範圍與中心頻率的除二注入鎖定除頻器，電路主要架構為一個使用N型金氧半電晶體的交錯耦合對之壓控振盪器，振盪器由五顆電感串連而成，加上一個並聯於共振腔用於注入訊號之N型金氧半電晶體，此晶片使用台積電矽鍺0.18微米製程，晶片面積為0.86×0.872 mm2，此電路工作電壓為1.1V，未注入訊號時中心頻率為3.13GHz，整體功耗為5.43mW。當注入訊號為0dBm時，其總鎖頻範圍為2.18GHz至8.25GHz，百分比為116.395%。
    第七章節描述第四個電路介紹兩個三共振三頻帶除三注入鎖定除頻器。此兩個注入鎖定除頻器皆使用不同參數但相同基礎架構的RLC振盪器與場效電晶體作為線性混波器。第一個注入式除三注入鎖定除頻起採用直接交叉耦合的振盪器架構，而另一個則使用具動態閘極偏壓電路的電容性交叉耦合振盪器架構。透過改變變容器上的偏壓，我們可以得到此兩個三頻帶除三注入鎖定除頻器的三個頻帶除頻範圍都能重疊。第一個三頻帶除三注入鎖定除頻器使用台積電矽鍺0.18微米製程，而第二個三頻帶除三注入鎖定除頻器則使用台積電0.18微米製程。
    第八章節描述第五個電路呈現一個寬鎖定範圍的除二注入鎖定除頻器，電路主要架構為互感耦合震盪振盪器。第一組電感使用兩圈的單路徑結構，而第二組電感為使用三路徑所構成，第二組電感以一組MOSFET作為開關。此晶片使用台積電矽鍺0.18微米製程，晶片面積為0.671×0.863 mm2，此電路工作電壓為0.7V，整體功耗為8.72mW。當注入訊號為0dBm時，其總鎖頻範圍為3.98GHz至12.71GHz，百分比為104.61%。

    This thesis presents four injection locked frequency dividers, the first one is a divider by 2 ILFD with a multi-path Inductor, the second one is a divide-by-2 ILFD with Transformer-Coupled resonator, the third is a divide-by-2 ILFD with Varactor-less, and the final one is a Multi-Resonance 3:1 divide-by-3 ILFD.
    In chapter 4, we studied divide-by-2 LC ILFDs using spiral inductors as distributed resonator to have multi-band locking range .Here we use single-path or 3-path inductors. The ILFDs can have two non-overlapped locking ranges. The two ILFDs were implemented in the TSMC 0.18 μm 1P6M CMOS process, the 1st die area is 1.122×0.898 mm2, and the 2nd die area is 1.058 × 0.862 mm2.
    In chapter 5, the second circuit is a divide-by-2 LC injection-locked frequency divider (ILFD) in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD with two non-overlapped locking ranges uses three pairs of varactors which are in shunt with the secondary inductor. By digital tuning the varactor, the tuning range and locking range can be varied. The die area is 0.688×1.008 mm2, it has small die area and two non-overlapped locking ranges.
    In chapter 6, we present a wide locking range divide range divide-by-two injection lock frequency divider using five on chip inductors. The ILFD uses cross coupled voltage-controlled oscillator (VCO) with one director injection MOSFET. The chip was implemented in the TSMC μm 1P6M CMOS process. The power consumption of the ILFD core is 5.43 mW and the locking range is from 6.07 GHz (116.395%) from 2.18 to 8.25 GHz at injection power Pinj=0 dBm. At the supply voltage of 1.1V, the divider’s free-running frequency is 3.13 GHz. The die area is 0.865×0.872 mm2.
    In chapter 7, we present two 3:1 ILFDs using triple-resonance RLC resonator. The two ILFDs use same RLC resonators with different device parameters and two injection MOSFETs used as linear mixers. One divide-by-3 ILFD uses direct-cross-coupled oscillator and the other 3:1 ILFD uses capacitive cross-coupled oscillator with dynamic gate bias circuit. Both of 3:1 ILFDs show overlapped locking ranges by switching gate bias of varactors or at a fixed bias. The first divide-by-3 ILFD was implemented in the TSMC μm 1P6M CMOS process and the other 3:1 ILFD was implemented in the TSMC standard 0.18 μm SiGe BiCMOS process.
    In chapter 8, we present a wide-band divide-by-2 injection-locked frequency divider (ILFD).The ILFD uses 3-path transformer-coupled resonator and the secondary inductor is turned on/off by a MOSFET switch . The secondary is made of a three-path inductor and the primary is made of a two-turn single-path inductor. The divide-by-2 ILFD was implemented in the TSMC μm 1P6M CMOS process. The power consumption of the ILFD core is 9.13mW and the locking range is from8.73 GHz (104.61%) from 3.98 to 12.71 GHz at injection power Pinj=0 dBm.

    中文摘要 I Abstract IV Table of Contents VII List of Figures IX List of Tables XIV Chapter 1 Introduction 1 1.1 BACKGROUND 1 1.2 THESIS ORGANIZATION 4 Chapter 2 OVERVIEWS OF OSCILLATORS 5 2.1 Introduction 5 2.2 BASIC THEORY OF OSCILLATORS 6 2.2.1 One-Port (Negative Resistance) View 7 2.2.2 Two-Port (Feedback) View 10 2.3 CLASSIFICATION OF OSCILLATORS 11 2.3.1 RESONATORLESS OSCILLATORS 12 2.4 PARALLEL RLC TANK 14 2.4.1 On Chip Inductor 15 2.4.2 On-Chip Varactors 23 2.4.3 RESONATORLESS OSCILLATORS 28 2.5 Phase Noise 31 2.5.1 Definition of The Phase Noise 31 2.5.2 Power and FOM 35 2.6 CLASSIFICATION OF OSCILLATORS 35 2.6.1 VCO CHARACTERISTIC PARAMETERS 36 2.6.2 QUALITY FACTOR 43 2.6.3 PULLING IN OSCILLATORS 46 2.6.4 TAIL CURRENT SOURCE 48 Chapter 3 Design of Injection Locked Frequency Divider 50 3.1 Introduction 50 3.2 Principle of Injection Locked Frequency Divider Figure Injection locked divider architecture 52 3.3 Locking Range 53 3.4 Direct ILFD 55 Chapter 4 LC Injection-Locked Frequency Divider with On-Chip Inductor as Distributed Resonator 57 4.1 INTRODUCTION 57 4.2 Circuit Design 58 4.3 Measurement and Discussion 61 Chapter 5 LC Injection-Locked Frequency Divider with Transformer-Coupled Resonator 68 5.1. Introduction 68 5.2. Circuit Design 69 5.3. Measurement Results 70 Chapter 6 Frequency Tuning and Locking Range of Varactor-less ÷2 Injection-Locked Frequency Divider 76 6.1 Introduction 76 6.2 Circuit Design 77 6.3 Measurement Results 78 Appendix 85 Chapter 7 Divider Multi-Resonance 3:1 Injection Lock Frequency Dividers 88 7.1 Introduction 88 7.2 Circuit Design 89 7.3 Measurement Results 92 Table 7-I: Performance Comparison of CMOS ÷3 LC ILFDs 97 Chapter 8 Double-Cross-Coupled Divide-by-2 Injection-Locked Frequency Dividers Using 3-path Transformer-Coupled Resonator 98 8.1 Introduction 98 8.2 Circuit Design 99 8.3 Measurement Results 100 Lock range GHz 110 Chapter 9 Conclusion 111 References 113

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    [87] Xuan-You Hang, the chip is fabricated in the TSMC 0.18 μm BiCMOS technology (T18-104A-E0063)
    [88] Li,Cheng-Lin, the chip is fabricated in the TSMC 0.18 μm SiGe BiCMOS technology (SiGe18-104D-E0007)
    [89] Fang,Meng-Yen, the chip is fabricated in the TSMC 0.18 μm SiGe BiCMOS technology (SiGe18-104B-E0009)
    [90] Fang,Meng-Yen ,the chip is fabricated in the TSMC 0.18 μm BiCMOS technology (T18-104C-E0038)
    [91] Yu Wen Huang, the chip is fabricated in the TSMC 0.18 μm BiCMOS technology (T18-106C-E0056)

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