簡易檢索 / 詳目顯示
| 研究生： |
程嵩浩 Sung-Hao Cheng |
|---|---|
| 論文名稱： |
24 GHz CMOS平衡式注入鎖定除三除頻器設計及其應用於除24除頻器之實現 Design of 24-GHz CMOS Balanced Divide-by-3 Injection-Locked Frequency Dividers and Their Applications to Implement Divide-by-24 Frequency Dividers |
| 指導教授： |
曾昭雄
Chao-Hsiung Tseng |
| 口試委員: |
曾昭雄
Chao-Hsiung Tseng 陳筱青 Hsiao-Chin Chen 瞿大雄 Tah-Hsiung Chu 張智林 Chih-Lin Chang |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2015 |
| 畢業學年度： | 103 |
| 語文別： | 中文 |
| 論文頁數： | 48 |
| 中文關鍵詞： | 高速除頻器鏈 、注入式鎖定除頻器 、主僕式除頻器 |
| 外文關鍵詞： | frequency divider link, injection-locked frequency divider, master-slave frequency divider |
| 相關次數： | 點閱：340 下載：7 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文係使用TSMC 0.18 μm CMOS製程研製應用於24 GHz鎖相迴路之高速除頻器鏈。除頻器鏈第一級採用平衡式注入鎖定除三除頻器，最大量測除頻相對頻寬為5.66 % (24 GHz~25.4 GHz)。使用峰化技術改良後之除頻器之最大量測相對除頻頻寬為7 % (22 GHz~23.6 GHz)。為使除頻鏈達到除24之功能，除第一級使用注入鎖定除三除頻器外，其後串接三級主僕式除二除頻器，並使用TSMC 0.18 μm CMOS製程實現。除24除頻器之量測最大鎖頻頻寬可達9.03 %(22.2 GHz~24.3 GHz)。此外，本論文研製之24-GHz可調式CMOS平衡式除24除頻器，量測最大鎖頻頻寬可達9.05 % (23.2 GHz~25.4 GHz)。
This thesis presents the frequency divider links for the 24-GHz phase-locked loop application. The developed frequency divider links are designed and fabricated using the TSMC 0.18 μm CMOS process. The balanced divide-by-3 injection-locked frequency divider (ILFD) is adapted to realize the 1st stage of the frequency divider link, and it achieves a locking range of 5.66 % (24 GHz~25.4 GHz). By using series-peaking technology, the ILFD achieves a locking range of 7 % (22 GHz~23.6 GHz).To obtain the divide-by-24 function, three stages of the divide-by-2 master-slave frequency dividers are connected with the ILFD to form a divide-by-24 frequency divider. It achieves a locking range of 9.03 % (22.2 GHz~24.3 GHz). As the tunable ILFD is applied to implement the 1st stage of the frequency divider link, one can obtain a locking range of 9.05 % (23.2 GHz~25.4 GHz).
[1]T. N. Luo and Y.-J. E. Chen, “A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 3, pp. 620-625, March 2008.
[2]C. H. Yu, J. H. Tsai, and T. W. Huang, “A low-power Ka-band frequency synthesizer with transformer feedback VCO embedded in 90-nm COMS technology,” IEEE of International Wireless Symp., pp. 1-4, April 2013.
[3]C. Cao, Y. Ding and O. K.K., “A 50-GHz phase-locked loop in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1649-1656, Aug. 2007.
[4]Y. H. Wong, W. H. Lin, J. H. Tsai, and T. W. Huang, “A 50-to-62 GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback,” IEEE RFIC 2008, pp. 435-438, Jun. 17.
[5]M. T., “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, Jul. 2004.
[6]J. H. Tsai, and H. D. Shih, “A 7.5 - 12 GHz divide-by-256/260/264/268 frequency divider for frequency synthesizers,” International Conf. Microwave and Millimeter Wave Technology, vol. 5, pp. 1-4, May 2012.
[7]A. Ghilioni, U. Decanis1, E. Monaco, A. Mazzanti, and F. Svelto, “A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz,” Proc. IEEE, pp. 282-284, Feb. 2011.
[8]W. S. Chang, K. W. Tan, and S. H. Hsu, “A 56.5–72.2 GHz transformer-injection miller frequency divider in 0.13 μm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 20, no. 7, pp. 393-395, Jul. 2010.
[9]Y. H. Kuo, J. H. Tsai, T. W. Huang, and H. Wang, “Design and analysis of digital-assisted bandwidth-enhanced miller divider in 0.18- μm CMOS process,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 12, pp. 3769-3777, Dec. 2012.
[10]H. R. Rategh, and T. H., “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813-821, Aug. 2012.
[11]K. H. Tsai, L. C. Cho, J. H. Wu, and S. I. Liu, “3.5mW W-band frequency divider with wide locking range in 90nm CMOS Technology,” Proc. IEEE ISSCC, pp. 466 -628, Feb. 2008.
[12]W. Choi and Y. Kwon, “Phase locked loop sub-circuits for 24 GHz signal generation in 0.5 μm SiGe HBT technology,” J. Semiconductor Technology and Science, vol. 7, no. 4, Dec. 2007.
[13]M. Huang, C.-H. Yu, J.-H. Tsai, and T.-W. Huang, "A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology," Pro. Asia Pacific Micro. Conf., pp. 643-645, Dec. 2012.
[14]C. H. Yu, J. H. Tsai, and T. W. Huang, “A low-power Ka-band frequency synthesizer with transformer feedback VCO embedded in 90-nm COMS technology,” IEEE International Wireless Symposium (IWS), pp. 1-4, Apr. 2013.
[15]B. Razavi, “A study of injection pulling and locking in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415 -1424, Sept. 2004.
[16]B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice-Hall, 1998, pp.182-183.
[17]P. H. Feng, and S. I. Liu, “Divide-by-three injection-locked frequency dividers over 200 GHz in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 405-416, Feb. 2013.
[18]“3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS,” Proc. IEEE Asian Solid-State Circuits Conf., pp. 93-96, Nov. 2011.
[19]C. Y. Wu, and C. Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 8, pp. 1649-1658, Aug. 2007.
[20]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001,
[21]A. Fard, and D. Aberg, “A Novel 18 GHz 1.3 mW CMOS Frequency Divider with High Input Sensitivity,” International Symposium on Signals, Circuits and Systems, 2005, vol. 2, pp. 409-412, Jul. 2005.
