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研究生： 張育苔
Yu-Tai Chang
論文名稱： 雙頻帶左手及右手壓控震盪器之設計
Design of Dual–Band Left–Handed and Right–Handed Resonator Voltage–Controlled Oscillators
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 徐敬文
Ching-Wen Hsue
吳乾彌
Chen-Mie Wu
莊敏宏
Miin-Horng Juang
徐世祥
Shih-Hsiang Hsu
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 105
中文關鍵詞： 壓控振盪器 、注入鎖定除頻器
外文關鍵詞： voltage-controlled oscillator, injection-locked frequency divider
相關次數： 點閱：314  下載：1 
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  •  上一筆

    • 在射頻收發機裡，鎖相迴路的特性非常重要，鎖相迴路內包含了頻率相位偵測器、充電幫浦、迴路濾波器、壓控振盪器、除頻器，為了追求低功耗，低相位雜訊，較寬的工作頻率範圍，其中又以壓控振盪器和除頻器特性最重要。
    首先，學生提出一低相位雜訊的CMOS壓控震盪器，其使用的是左手LC網路。此震盪器使用台積電0.18微米製程，晶片面積為0.688 × 0.832mm2。此電路使用了兩個單元的左手LC震盪器串聯同時讓LC震盪器並聯電路下方的交叉耦合以補償LC震盪器的損耗。使用一個差動開關來達成低頻帶。此震盪器為雙頻帶，高頻 (低頻)的可調範圍從5.683~6.031 (3.720~3.789) GHz，FOM為 –190.30 (–187.14) dBc/Hz。
    接著，我們呈現一個低相位雜訊的CMOS雙頻帶壓控震盪器，使用的是右手LC網路。其使用台積電矽鍺0.18微米製程，晶片面積為0.675×0.762 mm2。此電路使用了兩個單元的右手LC震盪器串聯同時讓LC震盪器並聯電路下方的交叉耦合以補償LC震盪器的損耗。使用一個差動開關來達成高頻帶。此震盪器為雙頻帶，低頻 (高頻)的可調範圍從4.222~4.519 (10.223~10.517) GHz，FOM為–191.40 (–185.07 ) dBc/Hz。
    再來，透過堆疊左手和右手LC震盪器來達成三頻帶壓控震盪器，此三頻帶壓控震盪器使用了左手震盪器堆疊在右手震盪器上，利用一對MOS組成開關以及可變電容來達到頻帶的切換。其使用台積電矽鍺0.18微米製程，高頻帶的功率消耗為3.69 mW，中頻帶的功率消耗為4.05 mW，低頻帶的功率消耗為3.30 mW。頻率的可調範圍為8.495~4.585 GHz，5.185~5.236 GHz，3.442~3.762 GHz。晶片面積為0.921× 1.063 mm2。
    最後，提出一個新穎寬鎖定範圍除四注入鎖定除頻器，使用台積電0.18微米製程。此除頻器利用交叉耦合與並聯LC共振腔之壓控震盪器，加上兩個注入MOS組成兩線性混波器。當驅動電壓為0.9 V 且注入強度為0 dBm，除四範圍可接受注入訊號從12.2 GHz 到 14.8 GHz，除頻大小為2.6 GHz，除頻比例為19.26 %。功率消耗為10.35 mW，晶片面積為1.026 ×0.943 mm2。

    In the RF transceiver, PLL characteristics are very important. PLL includes phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage controlled oscillator (VCO), and frequency divider (FD). This thesis studies design of VCO and frequency divider.
    Firstly, this thesis proposes a low phase noise CMOS dual–band voltage–controlled oscillator (VCO) using a left–handed (LH) LC network. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS process technology and the die area of the oscillator is 0.688 × 0.832 mm2. The VCO uses two units of a left–handed (LH) LC resonator stacked in series, and the LC resonator is in shunt with a pair of cross–coupled transistors to compensate for the loss of the LC resonator. A differential switched inverter is used to activate the low–frequency band. The VCO can generate differential signals in the high (low)–band frequency range of 5.683~6.031 (3.720~3.789) GHz. The measured high (low)–band figure of merit (FOM) is –190.30 (–187.14) dBc/Hz.
    Secondly, we present a low phase noise CMOS dual–band voltage–controlled oscillator (VCO) using a right–handed (RH) LC network. The proposed VCO has been implemented with the TSMC 0.18 μm SiGe BiCMOS process and the die area of the oscillator is 0.675×0.762 mm2. The VCO uses two units of right–handed (RH) LC resonator stacked in series, and the LC resonator is in shunt with a pair of cross–coupled transistors to compensate the loss of LC resonator. A differential switched inverter is used to activate the high–frequency band. The VCO can generate differential signals in the low (high)–band frequency range of 4.222~4.519 (10.223~10.517) GHz. The measured low (high)–band figure of merit (FOM) is –191.40 (–185.07) dBc/Hz.
    Thirdly, by exploiting the resonant frequencies in a stacked right–handed and left–handed LC resonators, a triple–band (TB) oscillator is designed. The TB oscillator using an LC resonator consists of a left–handed resonator stacked on a right–handed resonator. The oscillator uses a pair of MOS–mode switches and varactors used for frequency band selection. The proposed oscillator has been implemented with the TSMC 0.18 μm SiGe BiCMOS technology. The power consumption of the core high–band VCO is 3.69 mW. The power consumption of the core middle–band VCO is 4.05 mW. The power consumption of the core low–band VCO is 3.30 mW. The VCO can generate differential signals in the frequency range of 8.495~8.585 GHz, 5.185~5.236 GHz, and 3.442~3.762 GHz. The die area of the triple–band VCO is 0.921× 1.063 mm2.
    Finally, a novel wide locking range divide–by–4 injection–locked frequency divider (ILFD) is proposed in this thesis and was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide–by–4 ILFD is based on a cross–coupled voltage–controlled oscillator (VCO) with a parallel–tuned LC resonator. Two direct injection MOSFETs with a common injection gate serve as two linear mixers. At the drain–source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide–by–4 is 2.6 GHz, with the incident frequency is 12.2 GHz to 14.8 GHz. The core power consumption is 10.35 mW. The die area is 1.026 ×0.943 mm2.

    中文摘要 I Abstract III Table of Contents V List of Figures VII List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chpter 2 Overview of the Voltage–Controlled Oscillators 5 2.1 Introduction 5 2.2 Basic Theory of Oscillators 7 2.2.1 One–Port (Negative Resistance) View 7 2.2.2 Two–Port (Feedback) View 10 2.3 Design Considerations of Voltage Controlled Oscillator 13 2.4 Parallel RLC Tank 15 2.4.1 Quality Factor 16 2.4.2 Inductor Design 19 2.4.3 Transformer Design 24 2.4.4 Varactor Design 34 2.5 The Popular Resonator 41 2.5.1 Single Transistor Oscillator 42 2.5.2 Cross–Coupled Oscillator 45 2.5.3 Complementary Cross–Coupled Topology 46 2.6 Phase Noise 49 2.6.1 Defination of The Phase Noise 49 2.6.2 Power and FOM 54 Chpter 3 Design of Injection Locked Frequency Divider 55 3.1 Principle of Injection Locked Frequency Divider 56 3.1.1 Locking Range 58 3.1.2 Direct ILFD 60 Chapter 4 Low Phase Noise Dual–Band Left–Handed Resonator Voltage–Controlled Oscillator 62 4.1 Introduction 62 4.2 Circuit Design 64 4.3 Measurement Result 67 Chapter 5 Right–Handed Resonator Voltage–Controlled Oscillator With Switchable Inverter 71 5.1 Introduction 71 5.2 Circuit Design 72 5.3 Measurement Result 75 Chapter 6 A Triple–Band CMOS Oscillator Using Stacked Right–Handed and Left–Handed LC Resonators 80 6.1 Introduction 80 6.2 Circuit Design 81 6.3 Measurement Result 85 Chapter 7 Wide–Locking Range Divide–by–4 Injection–Locked Frequency Divider Using Frequency Doubler 91 7.1 Introduction 91 7.2 Circuit Design 92 7.3 Measurement Result 96 Chapter 8 Conclusion 99 References 101

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