研究生: |
陳廷維 TING-WEI Chen |
---|---|
論文名稱: |
貫穿差排對4H-SiC功率元件漏電效應之探討 Effects of the threading dislocations on the leakage current of 4H-SiC power devices |
指導教授: |
洪儒生
Lu-Sheng Hong |
口試委員: |
黃智方
Chih-Fang Huang 李坤彥 Kung-Yen Lee |
學位類別: |
碩士 Master |
系所名稱: |
工程學院 - 化學工程系 Department of Chemical Engineering |
論文出版年: | 2021 |
畢業學年度: | 109 |
語文別: | 中文 |
論文頁數: | 81 |
中文關鍵詞: | 碳化矽 、貫穿差排缺陷 、蕭特基二極體 、金氧半場效電晶體 、漏電 |
外文關鍵詞: | SiC, Threading dislocations, Schottky barrier diode, Metal-oxide-semiconductor field-effect transistor, leakage current |
相關次數: | 點閱:310 下載:3 |
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本研究針對碳化矽磊晶層中普遍存在的貫穿差排缺陷對功率元件漏電流的影響進行探討,透過對兩種常見的功率元件-蕭特基二極體(SBD)與金氧半場效電晶體(MOSFET)做為測試對象,以數量級超過數十至百顆的元件單位,追跡元件電性的差異與磊晶層內缺陷密度之間的關聯性。
首先在SBD的實驗中,我們發現貫穿刃差排(TED)相較於貫穿螺旋差排(TSD)對於元件在軟擊穿區域的漏電影響來得大。我們認為與擊穿厚度達5.5微米的碳化矽磊晶層成長方向平行存在之TED具有較TSD略小之功函數,造成在金半接面處能帶彎曲較大導致有利電子的穿隧,應可說明此漏電現象的差異。相對的,在MOSFET的分析實驗中卻發現,TSD對於源極到汲極的崩潰電壓(VB)顯現較明顯之不良影響。可能的原因為磊晶層表面TSD所誘發的奈米凹坑較TED寬且深而累積較高濃度的載子;或是因為在淺層離子佈植時於TSD處較易造成離子衝穿,而導致較易漏電的現象發生。
This study focused on investigating the impacts of the threading dislocations existing in the silicon carbide (SiC) epitaxial layers, on the leakage current of two kinds of power devices: Schottky barrier diode (SBD) and Metal-Oxide-Semiconductor-Field-Effect Transistor (MOSFET). The correlation between the electrical property differences of the device components and the defect density in the epitaxial layers was traced statistically according to a component units in the order of more than ten to a hundred of magnitude.
First of all, we found that threading edge dislocation (TED) showed a greater impact on the leakage current of the SBD in the soft breakdown regime than threading screw dislocation (TSD). This phenomenon is most plausibly related to the difference in surface potential between TED and TSD, both existing in the SiC epitaxial layer with a breakdown thickenss of 5.5 m. That is, TED site exhibited a smaller work function than TSD, resulting in a greater band bending at the junction area and therefore favorable for electron tunneling.
By contrast, TSD showed more adverse effects on the breakdown voltage (VB) of the source to drain rather than TED with respect to MOSFET. The wider and deeper pits structure induced by the TSD on the surface of the epitaxial layer may be responsible to the lowing of VB because of the more accumulated carriers at TSD site. In addition, in the process of ion implantation process to make p+ region for MOSFETs, ion punching through may easily occur at the TSD, resulting in more leakage current.
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