在過去50年來，隨著墨爾定律不停微縮電晶體。我們希望電晶體微縮到達每一個技術世代時，都能使得電路操作速度更快，同時具有更高的電路積極度。不過，隨著電晶體不停的微縮，要如何確保元件的可靠度以及功率損耗將變的更加困難。在此論文中，首先會簡短敘述目前在電晶體微縮上所遭遇的一些問題。另外，我們將利用TSUPREM4製程模擬軟體和MEDICI元件特性模擬軟體來模擬典型技術所製造而成的次零點一微米bulk MOSFET及SOI MOSFET，並且進一步討論這些技術在電晶體微縮上的影響。
在深次微米的電晶體中，我們常利用一些通道工程或者是汲極工程來改善我們元件的特性，常見的典型技術像是退後通道的離子植入、HALO離子植入以及袋狀離子植入。而透過這些技術的使用，深次微米電晶體中不理想的特性都能有效的改善。因此，當電晶體持續微縮到次零點一微米時，我們將試著透過這些技術繼續幫助我們達到高效能、高可靠度以及低功率損耗的目標。另外，我們也採用了double-diffused drain去製造次零點一微米的bulk MOSFET及SOI MOSFET，並且與前面所提及的技術作比較。
在我們研究過程中，發現不同的技術適用於不同的基板。例如，對於bulk MOSFET，通道離子植入搭配HALO離子植入或者袋狀離子植入將具有較佳的特性，這是由於此兩種技術將較其他技術具有較高的Ion/Isub比值和較低的接面電容值。另外，對SOI MOSFET而言，double-diffused drain會具有較佳的特性，這是由於double-diffused drain除了較其他技術具有較高的Ion/Isub比值外，還具有絕佳的抗punch-through能力。
In the past 50 years, we never stop shrinking MOSFETs is in order to follow Moore’s law. We hope scaling transistors in each technology generation can increase circuit speed and packing density. However, as the devices get smaller, ensuring their reliability and power dissipation become increasing difficult. In this project, we give a brief literature review on the subject of MOSFET scaling. Moreover, we use TSUPREM-4 process simulator and MEDICI device simulator to simulate sub-0.1μm bulk and SOI MOSFET formed by a lot of typical technologies, and further, we discuss these typical technologies effect on scaling MOSFET.
For channel and drain engineering, there are various kind of technology usually used in deep sub micron regime MOSFET, such as retrograde channel, halo doping, pocket implantation,…..,etc. And these approaches can improve the device characteristics effectively in deep sub micron regime MOSFET. Thus, even if the MOSFET reached the sub-0.1μm generation node, we hope these typical technologies can help us to fulfill the demands for high performance, high reliability and low power consumption. In addition, we also employ double-diffused drain to fabricate sub-0.1μm bulk and SOI MOSFET.
In this thesis, we find that the different typical technology is suitable for different silicon substrate. For example, the process schemes of Vt with halo implantation and Vt with pocket implantation may be more available for sub-0.1μm node bulk MOSFETs, because of relatively higher ratio of Ion/Isub and smaller junction capacitance. And the process scheme of double-diffused drain may be more available for sub-0.1μm node SOI n-MOSFETs, because of relatively higher ratio of Ion/Isub and excellent punch-through immunity.
Contents
Abstract(Chinese) I
Abstract III
Acknowledgements V
Figure Captions VIII
List of Tables XV
Chapter 1 Intruction 1
Chapter 2 The Description of Sub-0.1μm MOSFET 3
2-1 Challenges of Shrinking MOSFET 3
2-1-1 Short-Channel-Effects 3
2-1-2 Parasitic Junction Capacitance 10
2-1-3 Source/Drain Parasitic Resistance 11
2-2 Prevailing Technologies in Shrinking MOSFET 12
2-2-1 Reduction in Supply Voltages 12
2-2-2 Channel and Drain Engineering for MOSFETs 13
2-2-3 Gate Oxide Technology 17
2-3 Process Integration Issues 18
Chapter 3 Devices Fabrication and Results Discussion 32
3-1 Bulk MOSFET 32
3-1-1 Fabrication Bulk MOSFET by Typical Technologies 32
3-1-2 Results and Discussion 34
A. Direct Vt Adjust Implant for Channel Engineering 34
B. Double-Diffused Drain 35
C. Comparison of Different Typical Technologies 39
3-2 SOI MOSFET 41
3-2-1 Fabrication SOI MOSFET by Typical Technologies 41
3-2-2 Results and Discussion 43
A. Double-Diffused Drain 43
B. Comparison of Different Typical Technologies 46
Chapter 4 Conclusions 92
References 93
Figure Captions
Fig. 2-1 Schematic diagram for charge sharing model explaining the reduction of Vth due to the source/drain depletion regions. 19
Fig. 2-2 Schematic diagram for charge sharing model explaining the reduction of Vth due to the source/drain depletion regions. 20
Fig. 2-3 Show the band diagram of DIBL (Drain Induced Barrier Lowering). 21
Fig. 2-4 Summary of leakage current mechanisms of transistors. 22
Fig. 2-5 Tunneling of electrons through an MOS capacitor. (a) Energy-band diagram at flat-band condition. (b) Energy-band diagram with positive gate bias showing tunneling of electron from substrate to gate. (c) Energy-band diagram at negative gate bias showing tunneling of electron from gate to substrate [10]. 23
Fig. 2-6 Condition of the depletion region near the drain-gate overlap region of an MOSFET when (a) Surface is accumulated with low negative gate bias; and (b) n+ region is depleted or inverted with high negative gate bias [6]. 24
Fig. 2-7 Show the MOSFETs junction capacitance model. 25
Fig. 2-8 The projection of 2001 ITRS for physical gate length. SDE junction depth and maximum ratio of S/D parasitic resistance to the ideal channel resistance (Vdd/Idd) with CMOS technology scaling. 26
Fig. 2-9 Schematically illustrates the parasitic resistance components in a MOSFET structure. 27
Fig. 2-10 Schematic the channel engineering that affected by retrograde channel doping. 28
Fig. 2-11(a) Schematic the drain engineering that affected by halo doping. 29
Fig. 2-11(b) Schematic the drain engineering that affected by pocket implantation. 29
Fig. 2-12 Show the (a) Partially depleted SOI-MOS (PD SOI) and (b) Fully depleted SOI-MOS (FD SOI) devices [22]. 30
Fig. 3-1 The primary device fabrication procedure for the normal process. 48
Fig. 3-2 The primary device fabrication procedure for the halo and pocket process. 49
Fig. 3-3 The primary device fabrication procedure for only pocket adjusted process. 50
Fig. 3-4 The primary device fabrication procedure for the double diffusion process. 51
Fig. 3-5(a) Show the resultant depth profiles of boron for the samples formed by using the different channel implantation conditions of B+ (10kev, 2.11e13 cm-2), B+ (20kev, 2.88e13 cm-2), B+ (30kev, 5.14e13 cm-2). 52
Fig. 3-5(b) Show the threshold-voltage values as a function of channel length for bulk n-MOSFETs formed by using the different channel implantation conditions. 52
Fig. 3-5(c) The on-state current corresponding to Fig. 3-5(b) 53
Fig. 3-5(d) The off-state current corresponding to Fig. 3-5(b) 53
Fig. 3-5(e) Show the impact ionization current as a function of gate voltage for n-MOSFETs formed by using the different channel implantation conditions. 54
Fig. 3-6(a) Show the threshold-voltage values as a function of channel length for bulk n-MOSFETs formed by using different SDE dosage implantation conditions of P+ (43kev, tilt 80o, 1e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 2e14 cm-2). 56
Fig. 3-6(b) Show the off-state current corresponding to Fig. 3-6(a). 56
Fig. 3-6(c) Show the on-state current corresponding to Fig. 3-6(a) 57
Fig. 3-6(d) Show the gate induced drain leakage as a function of gate voltage for bulk n-MOSFETs formed by using different SDE dosage implantation conditions. 57
Fig. 3-6(e) Show the impact ionization current as a function of gate voltage for bulk n-MOSFETs formed by using different SDE dosage implantation conditions. 58
Fig. 3-7(a) Show the threshold-voltage values as a function of channel length for bulk n-MOSFETs formed by using different tilt angle implantation conditions of P+ (43kev, tilt 75o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 85o, 1.6e14 cm-2). 59
Fig. 3-7(b) The off-state current corresponding to Fig. 3-7(a). 59
Fig. 3-7(c) The on-state current corresponding to Fig. 3-7(a) 60
Fig. 3-7(d) Show the gate induced drain leakage as a function of gate voltage for bulk n-MOSFETs formed by using different tilt angle implantation conditions. 60
Fig. 3-7(e) Show the impact ionization current as a function of gate voltage for bulk n-MOSFETs formed by using different SDE dosage implantation conditions. 61
Fig. 3-8(a) Show the resultant depth profiles of phosphorus for the samples formed by the different tilt angle implantation conditions of P+ (43kev, tilt 75o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 85o, 1.6e14 cm-2). 62
Fig. 3-8(b) Show the surface electric field values at the drain extension region for the samples formed by using different tilt angle implantation conditions. 62
Fig. 3-9(a) Show the threshold-voltage values as a function of channel length for bulk n-MOSFETs formed by using different SDE implantation energy conditions of P+ (38kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (48kev, tilt 80o, 1.6e14 cm-2). 63
Fig. 3-9(b) The off-state current corresponding to Fig. 3-9(a). 63
Fig. 3-9(c) The on-state current corresponding to Fig. 3-9(a). 64
Fig. 3-9(d) Show the gate induced drain leakage as a function of gate voltage for bulk n-MOSFETs formed by using different SDE implantation energy conditions. 64
Fig. 3-9(e) Show the impact ionization current as a function of gate voltage for bulk n-MOSFETs formed by using different SDE implantation energy conditions. 65
Fig. 3-10(a) Show the resultant depth profiles of phosphorus for the samples formed by using the different SDE implantation energy conditions of P+ (38kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (48kev, tilt 80o, 1.6e14 cm-2). 66
Fig. 3-10(b) Show the surface electric field values at the drain extension region for the samples formed by using different SDE implantation energy. 66
Fig. 3-11(a) Show the threshold-voltage values as a function of channel length for bulk n-MOSFETs formed by using different typical technologies. 67
Fig. 3-11(b) The off-state current corresponding to Fig. 3-11(a). 67
Fig. 3-11(c) The on-state current corresponding to Fig. 3-11(a) 68
Fig. 3-11(d) Show the gate induced drain leakage as a function of gate voltage for bulk n-MOSFETs formed by using different typical technologies. 68
Fig. 3-11(e) Show the impact ionization current as a function of gate voltage for bulk n-MOSFETs formed by using different typical technologies. 69
Fig. 3-12(a) The lateral boron concentration at the surface region for devices formed by using different typical technologies. 72
Fig. 3-12(b) The boron profile for devices formed by using different typical technologies. 73
Fig. 3-12(c) The electric field values for devices formed by using different typical technologies. 74
Fig. 3-13 The primary process flow that fabricates the SOI n-MOSFETs. 75
Fig. 3-14(a) The primary device fabrication procedure for the halo process. 76
Fig. 3-14(b) The SOI n-MOSFET device fabrication procedure for only pocket adjusted process. 77
Fig. 3-15 The SOI n-MOSFET device fabrication procedure for the double diffusion process. 78
Fig. 3-16(a) Show the threshold-voltage values as a function of channel length for SOI n-MOSFETs formed by using different SDE dosage implantation conditions of P+ (43kev, tilt 80o, 1e14 cm-2), P+ (43kev, tilt 80o, 1.5e14 cm-2), P+ (43kev, tilt 80o, 2e14 cm-2) 79
Fig. 3-16(b) The off-state current corresponding to Fig. 3-16(a). 79
Fig. 3-16(c) The on-state current corresponding to Fig. 3-16(a) 80
Fig. 3-16(d) Show the gate induced drain leakage as a function of gate voltage for SOI n-MOSFETs formed by using different SDE dosage implantation conditions. 80
Fig. 3-16(e) Show the impact ionization current as a function of gate voltage for SOI n-MOSFETs formed by using different SDE dosage implantation conditions. 81
Fig. 3-17(a) Show the threshold-voltage values as a function of channel length for SOI n-MOSFETs formed by using different tilt angle implantation conditions of P+ (43kev, tilt 75o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 85o, 1.6e14 cm-2). 82
Fig. 3-17(b) The off-state current corresponding to Fig. 3-17(a). 82
Fig. 3-17(c) The on-state current corresponding to Fig. 3-17(a) 83
Fig. 3-17(d) Show the gate induced drain leakage as a function of gate voltage for SOI n-MOSFETs formed by using different tilt angle implantation conditions. 83
Fig. 3-17(e) Show the impact ionization current as a function of gate voltage for SOI n-MOSFETs formed by using different SDE dosage implantation conditions. 84
Fig. 3-18(a) Show the threshold-voltage values as a function of channel length for SOI n-MOSFETs formed by using different SDE implantation energy conditions of P+ (38kev, tilt 80o, 1.6e14 cm-2), P+ (43kev, tilt 80o, 1.6e14 cm-2), P+ (48kev, tilt 80o, 1.6e14 cm-2). 85
Fig. 3-18(b) The off-state current corresponding to Fig. 3-18(a). 85
Fig. 3-18(c) The on-state current corresponding to Fig. 3-18(a) 86
Fig. 3-18(d) Show the gate induced drain leakage as a function of gate voltage for SOI n-MOSFETs formed by using different SDE implantation energy conditions. 86
Fig. 3-18(e) Show the impact ionization current as a function of gate voltage for SOI n-MOSFETs formed by using different SDE implantation energy conditions. 87
Fig. 3-19(a) Show the threshold-voltage values as a function of channel length for SOI n-MOSFETs formed by using different typical technologies. 88
Fig. 3-19(b) The off-state current corresponding to Fig. 3-20(a). 88
Fig. 3-19(c) The on-state current corresponding to Fig. 3-20(a) 89
Fig. 3-19(d) Show the gate induced drain leakage as a function of gate voltage for SOI n-MOSFETs formed by using different typical technologies. 89
Fig. 3-19(e) Show the impact ionization current as a function of gate voltage for SOI n-MOSFETs formed by using different typical technologies. 90
List of Tables
Table I. Trade-off a lot of process parameters 31
Table II. illustrates the junction capacitance values for the samples formed by using the different channel implantation conditions of B+ (10kev, 2.11e13 cm-2), B+ (20kev, 2.88e13 cm-2), B+ (30kev, 5.14e13 cm-2). 55
Table III. illustrates the detailed results of physical gate length 50 nm bulk n-MOSFETs formed by different typical technologies 70
Table IV. illustrates the junction capacitance values of physical gate length 50 nm bulk n-MOSFETs formed by different typical technologies 71
Table V. illustrates the detailed results of physical gate length 50 nm SOI n-MOSFETs formed by different typical technologies 91
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