本研究第一部分實驗係利用一低溫鋁擴散於非晶矽膜層使其形成p型多晶矽層之技術，作為矽晶異質接合太陽電池背電場製作的應用。以此技術製備p型膜層的實驗結果顯示，非晶矽層與濺鍍鋁層接觸並經200℃熱處理1小時後，可獲得薄膜導電率為185 (S/cm)的結晶化p型膜層。以此低溫鋁擴散形成的p型層作為p型單晶矽晶異質接合太陽電池元件的背電場，獲得元件的光電轉換效率可達12.0 %。由穿透式電子顯微鏡觀察到此一製程會造成鋁擴散到矽基材的界面上而發生部分磊晶，導致元件開路電壓僅有590 mV。有鑒於此，我們使用局部鋁擴散以及加入擴散阻絕層的方式來提升元件的開路電壓，結果顯示使用氧化銦錫膜層作為阻絕層時，晶片暗示開路電壓可達700 mV。
第二部分的實驗中，我們利用低溫鋁擴散製程的技術於背向指叉式電極太陽電池的製作，期待能減少製程時所需的光微影技術與圖形定義的對準步驟，嘗試僅以一道圖形定義即可完成背面指叉型p-n接合的膜層。實驗結果顯示，藉由晶片背面全面先形成n型非晶矽層後，再以局部區域的低溫鋁擴散技術可成功製作出指叉型p+-n+區域，製作出的背向電極太陽電池元件的電流密度、開路電壓、填充因子分別為18.03 mA/cm2、523 mV、45.1 %，元件效率為4.26 %

We have explored a process to form highly Al-doped crystalline Si layers through low-temperature diffusion of Al into hydrogenated amorphous Si (a-Si:H) layers prepared by PECVD. A typical film conductivity of ~185 (S/cm) was obtained after thermal-treating Al/a-Si:H for 1 hr at 200oC. Applying the p+ layer thus prepared as the back surface field for p-type mono-crystalline Si hetero-junction solar cell, we achieved a primary cell efficiency of 12.0 % on an untextured Si wafer with an open circuit voltage (Voc) of 590 mV. In particular, unintentional epitaxial growth was found to occur during an intended Al-doped crystalline process, thereby deteriorating the interfacial passivation because of the poor structural quality of nanocrystalline Si. Then, we investigated the possibility to insert a diffusion barrier layer to prevent the interdiffusion of Al into amorphous Si matrix, by which the implied Voc was improved from 590 mV to 695 mV. Moreover, Interdigitated back contact silicon solar cell was fabricated by applying the present technique, which showed a preliminary cell efficiency of 4.26%.

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