本論文主要目標在於提出一種構建多元件高精度匹配佈局的方法。使用這種方法，工程師將有更大的自由度，依據其創新和電路準確度，來選擇佈局模式。
本論文設計了一顆14位元電流導向式數位至類比資料轉換器來驗證提出的佈局。這顆14位元電流導向式數位至類比資料轉換器採用混合架構，高位元部分的8位元使用溫度計碼編碼方式，透過一顆解碼器將二進位權重碼解碼為溫度計碼來控制電流源矩陣，該電流源矩陣使用高精度匹配佈局來消除系統性不匹配的影響，同時根據蒙地卡羅模擬確定合適的電流源尺寸，並透過佈局自動化實現電流源矩陣的佈局。低位元部分的6位元使用二進位元權重式編碼方式，透過本論文提出的電流源分割架構，在增加精度的同時保持較快的速度。
此數位至類比資料轉換器設計是由TSMC 0.18um Mixed-Signal 1P6M製程實現，可以工作在1.8V與2.7V的供應電壓下，後模擬INL 0.034LSB，轉換速率200MHz，晶片核心面積6.62mm2。

A general methodology to construct highly matched layout pattern for multiple-device is proposed in this thesis. With these general methodologies, engineers will have more degrees of freedom for choosing layout pattern according to their innovations and the degree of circuit precision.
This thesis Design a 14-bit high accuracy current-steering DAC to implement proposed layout pattern. The DAC presented is segmented architecture. The eight most significant bits are decoded from binary to thermometer code in the thermometer decoder, which steers the unary weighted current source array. The Systematic mismatch of this current source array is canceled by highly matched layout pattern. The size of transistor is decided though Monte Carlo simulation , and the layout of current source array made by Layout automation. The six bit least significant bits are implemented by a current divided circuit proposed by this thesis to enhance accuracy and update rate.
The DAC would be integrated in TSMC 0.18um Mixed-Signal 1P6M process, running from 2.7V power supply. The integral nonlinearity of post-simulation is 0.034LSB, update rate is 200 MHz and the chip core area is 6.62mm2.

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