回顧過去，類比積體電路的論文側重設計而非佈局。即便在積體電路佈局論文中，主要的研發重點在於創新關鍵元件的佈局模式，以減少系統不匹配的衝擊進而提高積體電路的良率。只有非常少數的論文著重在關鍵元件的面積配置，藉以降低隨機不匹配的影響。於西元2006年，好不容易出現一篇有關元件面積配置的優秀論文。然而，此面積配置方法以個案列舉方式逐一討論，不但只能以固定某些特定參數值的方式來模擬應證，更欠缺沒有令人信服的理論推導，以證明該些面積配置方法的正確性。為此，本論文的重點在於研究以貼近關鍵元件權重的方式來實施面積配置，以得到或逼近以積分非線性誤差為計算基礎之最佳良率。為了證明我們的方法確實有效，我們將列舉一些重要且極具代表性的類比電路，來進行面積配置的全面模擬與理論分析。此外，本論文亦以台積電 0.35μm的製程實現一R-2R ladder階梯網路之測試電路，以測量結果來證實基於元件權重面積配置方法的優越性。最後，當IC設計者在面對新的類比電路時，若對製程變異模型、良率估計了解不深，也能夠依照論文基於此權重面積配置的經驗法則來實現高良率佈局，可大幅減輕IC設計者的負擔。

In the past, analog integrated-circuit (IC) papers focused much less on the layout than design. Among those IC layout papers, most attention were paid to the layout patterns of critical devices to reduce the systematic mismatch for yield enhancement in analog integrated circuits. Even less of them focused on area allocation to minimize the impact of random mismatch for yield optimization. In 2006, an excellent layout paper dedicated for area allocation was finally presented. However, the area allocation strategies were presented in a case-by-case basis and verified by selected simulations around the optimum only. To make matters worse, no convincing theoretical deduction was given to prove the correctness of those strategies. This thesis focus on area allocation strategy based on the device weight for the close-to-optimum integral non-linearity (INL)-based yield in integrated circuits. To demonstrate this strategy, not only full-coverage simulation but also theoretical analysis of area allocations will be given for some important representative analog circuits. Moreover, a test chip of R-2R ladder circuits has been realized in a TSMC 0.35μm standard CMOS process to verify the excellence of the weight based area allocation strategy. Finally, as a byproduct, a rule of thumb for weight-based device area allocation for close-to-optimum INL-based yield will be presented to significantly ease the burden of IC designers who know not much about process variation modeling or yield estimation when facing new analog circuits.

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