本論文設計一個十位元電流導向式之數位至類比轉換器，該轉換器的主要實現架構有三種，分別為單位電流源矩陣、二進位權重式與分段式架構。而本論文採用二進位權重電流導向式架構來實現，考量電路會受到操作電壓、短通道調變效應(Short-Channel Effect)與佈局不匹配等影響，導致電流源陣列之輸出電流難以精準設計，我們提出一種全新的複製-分割分流器架構，只需專注匹配各個位元的電流源，並藉由二階梯度消除(2nd Order Gradient Cancellation)與三階梯度消除(3rd Order Gradient Cancellation)的佈局技巧，抑制系統性不匹配(Systematic Mismatch)的影響，以獲得高精度的電流輸出。
此數位至類比轉換器使用TSMC 90nm 1P9M製程來實現，操作於1.2V的供應電壓下，積分非線性誤差(INL)介於+0.04 LSB ~ -0.03 LSB，微分非線性誤差(DNL)介於+0.07 LSB ~ -0.02 LSB。當輸入頻率為499.76MHz時，無突波動態範圍(SFDR)為61dB，功率消耗為24 mW，核心晶片面積為0.25 mm2。

A 10-bit 1GS/s digital-to-analog converter is prosed and implemented in this thesis. Conventionally, there are three major architectures for implementation: Unary Current Source Matrix, Binary-Weighted and Segmented Current-Steering DAC. The Binary-Weighted Current-Steering DAC is adopted in this thesis to reduce the realization complexity. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough binary-weighted current source array. A newly-proposed current-splitter architecture along with the 2nd to 3rd order gradient cancellation layout is utilized to ensure the required accuracy and ease the circuit design.
The DAC is implemented in a TSMC 90 nm 1P9M CMOS technology powered with 1.2V supply. The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be +0.04 ~ -0.03 LSB and +0.07~ -0.02 LSB respectively. With 499.76MHz input sine wave, the spurios free dynamic range (SFDR) is 61 dB. The power consumption is 24 mW and the active area is merely 0.25 mm2.

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