簡易檢索 / 詳目顯示

回結果列表
研究生： 謝仁翔
Jen-Hsiang Hsieh
論文名稱： 新式注入鎖定除頻器之設計與其熱載子應力效應
Design and Hot Carrier Stress Effect ofNovel Injection-Locked Frequency Divider
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 徐敬文
Ching-Wen Hsue
黃進芳
Jhin-Fang Huang
馮武雄
Wu-Shiung Feng
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 114
中文關鍵詞： 壓控振盪器 、除頻器 、熱載子應力效應
外文關鍵詞： VCO, Divider, Hot Carrier Stress Effect
相關次數： 點閱：204  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  •  上一筆

    • 在射頻收發機裡，PLL的特性非常重要，PLL內包含了頻率相位偵測器、充電幫浦、迴路濾波器、壓控振盪器、除頻器，為了追求低功耗，低相位雜訊，較寬的工作頻率範圍，其中又以壓控振盪器和除頻器特性最重要。
    首先，本論文呈現兩個除三注入鎖定除頻器。第一個電路裡，我們利用內部迴授來增強除頻鎖定範圍，此ILFD使用台積電矽鍺0.18微米製程，功耗為13.2 mW在直流偏壓為0.8V時。而頻率可調範圍為3.079~3.163 GHz，在注入能量0dBm時的除頻範圍為8.9~10.8 GHz (19.28%)，操作頻率範圍為8.9~11 GHz (21.1%)，晶片面積為0.620×0.871 mm2。
    其次，我們呈現一個兩次混波除三注入鎖定除頻器，此ILFD使用台積電0.18微米製程，功耗為11.496 mW在直流偏壓為0.8V時。而頻率可調範圍為4.32~3.78 GHz，在注入能量0dBm時的除頻範圍為10.5~13.5 GHz (25%)，操作頻率範圍為9.9~13.5 GHz (30.76%)，晶片面積為0.659×0.887 mm2。
    再來，我們將這兩個電路個別去做熱載子應力效應對電路架構的不同影響，如phase noise，locking range，current，tuning range，並且去做分析與探討。
    最後，我們呈現一個三頻帶壓控振盪器，此壓控振盪器使用台積電0.18微米製程，功耗為3.735 mW在直流偏壓為0.75V時。此壓控振盪器可以產生差動訊號的頻帶分別為6.98~7.41GHz，5.28~5.31 GHz， 4.27~4.49 GHz，晶片面積為0.568×1.189 mm2。

    In the RF transceiver, PLL characteristics are very important, PLL to including Phase Frequency Detector (PFD),Charge Pump (CP),Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide operating frequency range, Among them, the most important performance of the VCO and Divider.
    First, this thesis presents two divider-by-3 injection locked frequency dividers. In the first circuit, we use internal feedback to enhance locking frequency, the ILFD was implemented with the TSMC 0.18 μm SiGe 3P6M BiCMOS process, and the core power consumption is 13.2 mW at the dc drain-source bias of 0.8 V. and tuning range is from 3.079 to 3.163 GHz. At the input power of 0 dBm, the locking range is from 8.9 GHz to 10.8 GHz (19.28 %), the operation range is from 8.9 to 11 GHz(21.1%), and the die area is 0.620 * 0.871 mm2.
    Secondly, we presents a mixer twice in divider-by-3 injection locked frequency dividers, the ILFD was implemented with the TSMC 0.18 μm 1P6M CMOS process, and the core power consumption is 11.496 mW at the dc drain-source bias of 0.8 V. The tuning range is from 4.32 to 3.78 GHz, At the input power of 0 dBm, the locking range is from 10.5 GHz to 13.5 GHz (25 %), while the operation range is from 9.9 to 13.5 GHz(30.76%), The die area is 0.659 * 0.887 mm2.
    Then, we measure hot carrier stress effects on the different parameters of these two circuit of circuit architecture, such as phase noise, locking range, current, tuning range, we do analysis and discussion for the measured result.
    Finally, we presents a Triple-Band Voltage-Controlled Oscillator, the VCO was implemented with the TSMC 0.18 μm 1P6M CMOS process, and the core power consumption is 3.735 mW at the dc drain-source bias of 0.75 V. The VCO can generate differential signals in the frequency range of 6.98-7.41GHz, 5.28-5.31GHz, and 4.27-4.49GHz. The die area is 0.568*1.189 mm2.

    Abstract III 誌謝 V Table of Contents VI List of Figures VIII List of Tables XII Chapter 1 Introduction 1 1.1 Background 1 1.2 Research Motivation 2 1.3 Thesis Organization 4 Chapter 2 Overview of the Voltage-Controlled Oscillators 6 2.1 Introduction 6 2.2 The Oscillators Theory 8 2.2.1 Feedback Oscillators 8 2.3 The Classification of Oscillators 13 2.3.1 Ring Oscillator 13 2.3.2 LC-Tank Oscillator 15 I. Colpitts and Hartley Oscillators 19 II. Negative -Gm Oscillators 20 2.4 Varactor and Transformer Design in VCO 22 2.4.1 Capacitor Design 22 2.4.2 Varactor Design 23 2.4.3 Transformer 27 2.4.3.1 Planar transformer 29 2.4.3.2 Stacked transformer 30 2.5 The parameters of VCO 32 2.5.1 RF Center Frequency[Hz] 32 2.5.2 RF Output Signal Power [dBm] 32 2.5.3 Power Dissipation [mW] 32 2.5.4 Harmonic/spurious [dBc] 32 2.5.5 Phase Noise 33 2.5.6 Tuning Range 36 2.5.7 Tuning Sensitivity [Hz/V] 37 2.5.8 Quality Factor 37 2.5.9 Figure of Merit [dBc/Hz] 40 Chapter 3 Design of Injection Locked Frequency Divider 42 3.1 Principle of Injection Locked Frequency Divider 43 3.1.1 Locking Range 45 Chapter 4 A Wide-Locking ÷3 BiCMOS Injection-Locked FrequencyDivider Using Internal Feedback 49 4.1 Introduction 49 4.2 Ciricuit Design 51 4.3 Measurement results 54 Chapter 5 A Wide-Locking Range ÷3 Injection-Locked Frequency Divider Using Concurrent Injection Mechanisms 58 5.1 Introduction 58 5.2 Ciricuit Design 60 5.3 Measurement results 65 Chapter 6 Hot-Carrier Effect on a Divide-by-3 Injection-Locked Frequency Divider 69 6.1 Introduction 69 6.2 Ciricuit Design 70 6.3 Measurement results 73 Chapter 7 RF Performance Degradation in CMOS Divide-by-3 Injection-Locked Frequency Divider due to Hot Carrier Effects 80 7.1 Introduction 80 7.2 Ciricuit Design 81 7.3 Measurement results 85 Chapter 8 Triple-Band Voltage-Controlled Oscillator Using Composite Left-handed LC Network Ended with Parallel-tuned LC Resonator 93 8.1 Introduction 93 8.2 Ciricuit Design 94 8.3 Measurement results 99 Chapter 9 Conclusion 104 References 106

    [1] J. Roggers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House, 2003.
    [2] B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
    [3] S. Smith, “Microelectronic Circuit 4th edition,” Oxford University Press 1998.
    [4] Behzad Razavi Design of Integrated Circuits for Optical Communications, Mc Graw Hill.
    [5] 林曉彤, 莊惠如, “應用於無線通訊之CMOS 射頻微機電開關及2-GHz/5-GHz 壓控振盪器RFIC之研究” 2004.06.
    [6] B. Razavi, Design of Analog CMOS Integrated Crcuits, MC Graw Hall,2001.
    [7 ] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
    [8] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
    [9] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
    [10] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
    [11] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179−194, Feb. 1998.
    [12] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC Oscillators,” IEEE Custom Integrated Circuits Conference, 2000, pp. 569−572.
    [13] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326−336, Mar. 2000.
    [14] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
    [15] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
    [16] D. Hauspie, E.-C. Park, and J. Craninckx, “Wide-band VCO with simultaneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007.
    [17] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
    [18] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
    [19] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
    [20] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
    [21] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
    [22] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
    [23] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
    [24] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
    [25] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
    [26] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
    [27] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon- based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
    [28] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
    [29] S.-L. Jang, R.-K. Yang, C.-C. Liu, and C.-W. Hsue, “A low power SiGe BiCMOS series-tuned divide-by-3 injection locked oscillators,” Micro. and Opt. Tech. Lett., vol. 51, no.9, pp. 2239−2242, Sept. 2009.
    [30] C.-C. Liu, C.-C. Wang, S.-L. Jang, and M.-H. Juang, ” A SiGe injection-locked-oscillator using HBT injector operated in saturation region,” Micro. and Opt. Tech. Lett., pp.734-737, April, 2011.
    [31] V. Jain, B. Javid, and P. Heydari, "A BiCMOS dual-band millimeter-wave frequency synthesizer for automotive radars," IEEE J. Solid State Circuits, vol.44, no.8, pp.2100-2113, Aug. 2009.
    [32] C.-C.Wang, Z. Chen, V. Jain, and P. Heydari, “Design and analysis of a silicon-based millimeter-wave divide-by-3 injection-locked frequency divider,” in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems, Jan. 2009.
    [33] H. Seo, J. Yun and J.-S. Rieh, ”SiGe 140 GHz ring-oscillator-based injection-locked frequency divider,” Electronics Letters(2012), 48(14):847
    [34] S.-L. Jang, C.-W. Hsu, C.-W. Chang and C.-W. Hsue, ” Wide-band 3 injection locked frequency divider in 0.35 μm SiGe BiCMOS,” Micro. and Opt. Tech. Lett., pp.609-611, March, 2011.
    [35] S.-L. Jang, C.-W. Chang, C.-L. Cheng, C.-W. Hsue, and C.-W. Hsu, " A wide-locking range SiGe BiCMOS divide-by-3 injection-locked oscillator,” IEEE Int. VLSI- DAT, 2011. pp.1-4.
    [36] S.-L. Jang, C.-C. Shih, C.-W. Chang, C.-C. Liu, and J.-F. Huang, ” A dual-band divide-by-2 injection locked frequency divider in 0.35 μm SiGe BiCMOS,” Micro. and Opt. Tech. Lett.., pp.2762-2765, Dec., 2010.
    [37] S.-L Jang, C. C. Liu and C.-W. Chung, ” A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., pp. 236-238, April, 2009.
    [38] H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp.27–29.
    [39] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang, “Divide-by-3 LC injection locked frequency divider implemented with 3D inductors,” IEICE Trans. Electron., vol. E91-C, no. 6, pp. 956–962, Jun. 2008.
    [40] X. P. Yu, H. M. Cheema, R. Mahmoudi, A. v. Roermund, and X. L. Yan, “A 3 mW 54.6 GHz divide-by-3 injection locked frequency divider with resistive harmonic enhancement,” IEEE Microw. Wireless Compon. Lett., pp.575-577, Sept. 2009.
    [41] S.-L. Jang, C.-W. Tai, and C.-F. Lee, “Divide-by-3 injection locked frequency divider implemented with active inductor,” Microwave and Optical Technology Lett., vol. 50, no. 6, pp. 1682–1685, June, 2008.
    [42] S.-L. Jang, C.-Y. Lin, and C.-F. Lee, “A low voltage 0.35 μm CMOS frequency divider with the body injection technique,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 7, pp.470–472, July 2008.
    [43] S.-L. Jang, and C.-W. Chang, ” A 90nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.229-231, April, 2010.
    [44] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.390-392, July, 2010.
    [45] S.-L. Jang, Y.-S. Chen, C.-W. Chang and C.-C. Liu,” injection-locked frequency dividing apparatus”, US patent # US008305116B2, 2012.
    [46] S.-L. Jang, C.-C. Liu, and J.-F. Huang, ” Divide-by-3 injection-locked frequency divider using two linear mixers,” IEICE Trans. on Electron., Vol.E93-C,No.1,pp.136-139, Jan. 2010.
    [47] Razavi, B., "A study of injection locking and pulling in oscillators," IEEE J. Solid-. State Circuits, vol.39, no.9, pp. 1415-1424, Sept. 2004.
    [48] Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 160–67, 2012.
    [49] S.-L. Jang and C.-Y. Chuang, ” Wide-locking range ÷3 series-tuned injection-locked frequency divider,” published online, Analog Integr Circ Sig Process., 2013.
    [50] J. Chung, K. N. Quader, C. G. Sodini, P. K. Ko, and C. Hu, "The effect of hot electron degradation on analog MOSFET performance," IEDM Dig., p. 553, 1990.
    [51] S.-S. Liu, S.-L. Jang, and C.-G. Chyau, " Compact LDD nMOSFET degradation model," IEEE Trans. Electron Devices, Vol. 45, No. 7, pp.1538-1547, 1998.
    [52] Dunn et al., “Foundation of rf CMOS and SiGe BiCMOS technologies,” IBM J. Res. Dev. 47(2/3), 101 (2003) 90.
    [53] H. Wu and A. Hajimiri, “A 19 GHz 0.5mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE Int. Solid-State Circuits Conf., pp. 412-413, Feb. 2001.
    [54] H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp.27–29.
    [55] S.-L. Jang and C.-Y. Chuang, ” Wide-locking range ÷3 series-tuned injection-locked frequency divider,” published online, Analog Integr Circ Sig Process., 2013.
    [56] H. Tsai and T. P. Ma, “l/f noise in hot carrier damaged MOSFETs: Effects of oxide charge and interface traps,” IEEE Electron Device Lett., vol. 14, pp. 256-258, 1993

    [57] Z. Jin; J. D Cressler; W. Abadeer; X. Liu; M. Hauser, and A. J. Joseph, “Hot carrier stress induced low-frequency noise degradation in 0.13μm and 0.18 μm RF CMOS technologies,” IEEE Int. Reliability Physics Symp., 2004, pp. 440 – 444.
    [58] E. Sheehan, P. K. Hurley, and A Mathewson,”Hot carrier degradation mechanisms in sub-micron p channel MOSFETs: Impact on low frequency (1/f) noise behaviour,” Microelectronics Reliability, vol. 38, no. 6, pp. 931-936(6), June 1998.
    [59] C. H. Ling, D. S. Ang, and S. E. Tan, “Effects of measurement frequency and temperature anneal on differential gate capactitance spectra observed in hot carrier stressed MOSFETs,” IEEE Electron Devices, vol. 42, no. 8, pp. 1528-1535, August 1995.
    [60] C. Dai, S.V. Walstra, S.-W. Lee, “The effect of instrinc capacitance degradation on circuit performance,” Symp. VLSI Technology, 1996, 196-197.
    [61] C. H. Ling, D. S. Ang, and S. E. Tan, “Effects of measurement frequency and emperature anneal on differential gate capactitance spectra observed in hot carrier stressed MOSFETs,” IEEE Electron Devices, vol. 42, no. 8, pp. 1528-1535, Aug. 1995.
    [62] S. Y. Huang, K. M. Chen, G.W. Huang, D. Y. Yang, C. Y. Chang, V. Liang, and H. C. Tseng, “Impact of hot carrier stress on RF power characteristics of MOSFETs,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., 2005, pp. 161–164.
    [63] S. Verma, H. R. Rategh, and T. H. Lee, “A unified model for injection locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 38, no. 6,pp. 1015–1027, Jun. 2003.

    [64] J. Jeong, S. Kim, W. Choi, H. Noh, K. Lee, K. S. Seo and Y. Kwon, “W-band divide-by-3 frequency divider using 0.1μm InAIAs/InGaAsmetamorphic HEMT technology,” Electronics Letts., vol. 41 no. 18, pp.1005 -1006, Sep. 2005.
    [65] M. Motoyoshi and M. Fujishima, “43μW 6GHz CMOS divide-by-3 frequency divider based on three-phase harmonic injection locking,” in Solid-State Circuits Conf. pp. 183-186, Nov. 2006.
    [66] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang, ” Divide-by-3 LC injection locked frequency divider implemented with 3D inductors,” IEICE Trans. Electronics., Vol.E91-C, No.6, pp.956-962, Jun. 2008.
    [67] S.-L. Jang and C.-Y. Chuang, ” Wide-locking range ÷3 series-tuned injection-locked frequency divider,” published online, Analog Integr Circ Sig Process., 2013.
    [68] B. Razavi, "A study of injection locking and pulling in oscillators," IEEE, J. Solid-. State Circuits, vol.39, no.9, pp. 1415-1424, Sept. 2004.
    [69] C T Hsu, M M Lau, Y T Yeow, and Z Q Yao, “Analysis of hot-carrier-induced degradation in MOSFETs by gate-to-drain and gate-to-substrate capacitance measurements”, in Proceed. 38th Annual Inter. Reliability Physics Symp., pp. 98-102, Apr. 2000.
    [70] N. Buadana and E. Socher, “A triple band travelling wave VCO using digitally controlled artificial dielectric transmission lines,” IEEE Radio Frequency Integrated Circuits Conference (RFIC 2011), June 2011, Baltimore.
    [71] Y. Itoh and S. Tanaka, “A triple-band SiGe HBT differential VCO using a reconfigurable multi-band resonator”, Proceeding of the 40th European Microwave Conf. pp. 456-459, Sept. 2010.
    [72] S.-L. Jang, Y.-T. Chen, C.-W. Chang and M.-H. Juang, ” Triple-band CMOS voltage-controlled oscillator,” Microw. Opt. Technol. Lett.., vol. 55, 4, pp.737-740, April. 2013.
    [73] S.-L. Jang, W.-H. Lee, and C.-W. Hsue, ” Fully-integrated standing wave oscillator using composite right/left-handed LC network,” Microw. Opt. Technol. Lett., vol. 55, 5, pp.985-988, May. 2013.
    [74] S.-L. Jang, H.-H. Lin and C.-W. Hsue,” Mode-switching left-handed standing wave voltage-controlled oscillator,” Microw. Opt. Technol. Lett. vol. 55, 9, pp. 1977–2244, Sept. 2013.

    無法下載圖示 全文公開日期 2018/07/26 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館：臺灣博碩士論文系統)
    QR CODE