視訊編碼技術H.264/AVC採用了許多的技術，使得編碼效率比之前標準提升至少50%，因此是最普遍的編碼標準。但是其中的移動估測運算複雜度佔整體視訊編碼的50-90%，是非常高的計算複雜度，會造成即時編碼系統設計上的瓶頸，因此有許多方法被提出來解決這個問題，然而許多演算法並不適合硬體實現，同時也會造成編碼效能下降的問題。
現有截斷位元像素 (Pixel Truncated) 搜尋演算法，利用降低運算的位元數來降低移動估測運算時的負載與功率消耗，但會導致編碼後的影像品質下降，於此演算法下會使用兩種匹配準則進行影像品質修正，因此在硬體實現上，會使用兩套匹配準則電路進行運算，造成硬體設計上的浪費。截斷像素需要讀取參考記憶體全部的位元資訊再進行資料截斷，這導致參考記憶體存取功率消耗增加。
本研究提出了一個複合式搜尋演算法，其包含二階段的搜尋，結合了截斷位元像素的技術以及搭配複合匹配準則架構來實行兩階段的搜尋，使用同一種運算架構進行兩種匹配準則的運算，達到硬體成本的降低，並在不同階段下使用不同的影像位元來存取切割字元線記憶體 (Divided Word-line Memory)，使記憶體存取功率消耗約降低60%，而影像品質失真的部分，經PSNR比較，最多下降0.021 dB，位元率增幅大多在3.9% 以下，整體效能非常貼近傳統全搜尋法的移動估測。
硬體架構的部分，為了符合即時編碼的需求，本研究採用8組一維的平行處理單元陣列設計。硬體實作使用TSMC 90 nm 1P9M 製程，操作頻率為267 MHz，邏輯閘總數為120.1 K，可支援HD 720p的即時編碼視訊，設定參考畫面為1張。

For the video coding standard H.264/AVC, many techniques are used for improving the coding efficiency. H.264/AVC provides 50% improvement in compression efficiency as compared to its precedent standard MPEG-4. However, motion estimation occupies 50-90% of the total computation complexity for video compression. This situation forms the main bottleneck for real-time video encoding. Therefore, there are many algorithms proposed to solve this problem. However, some of these algorithms are not suitable for hardware implementation and also causes loss of coding efficiency.
Currently used pixel truncated search algorithms can be used to reduce the computational load and power consumption by reducing the number of computation bits. Although it leads to the degrading of picture quality, it can further use two matching criterions to enhance the picture quality. In hardware implementation, it needs two extra circuits for calculating the matching criterions and thus incurs additional hardware overhead. Besides, the reference memory is accessed with full bits before truncating. This access scheme inevitably increases the power consumption of memory access.
In this thesis, a hybrid two-step search algorithm which combines both the pixel truncation technique and the hybrid matching criterions is proposed. The corresponding VLSI architecture for implementing the proposed two-step search algorithm is also presented. The proposed architecture can calculate the two matching criterions by using the same processing elements and thus reduce the hardware overhead. Moreover, a novel divided word-line (DWL) memory architecture is used for accessing the required bits in each search step. It can save memory access power for about 60%. For the picture quality, the PSNR drop is less than 0.021dB and the increasing of bitrate is less than 3.9%. The achieved coding performance is very close to the conventional full search algorithm.

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