近年來由於製程技術的進步，行動裝置與物聯網得以迅速發展，對於非揮發性記憶體的需求也隨之上升，現今電阻式記憶體相較快閃式記憶體，擁有更低的功耗、更快的存取操作與更小的晶片面積，且其特殊的物理結構能執行矩陣運算，因此被大量運用在人工智慧技術當中。由於電阻式記憶體的製程技術仍尚未成熟，使得記憶體的耐久度與良率嚴重下降，在過去常用來解決這個問題的是錯誤更正碼技術，然而，電阻式記憶體中的錯誤會隨著使用時間累積，在一定時間後，編碼字中的錯誤將超過錯誤更正碼之保護能力，使得記憶體無法順利被修復。
為了解決上述的問題，本篇依照電阻式記憶體中的故障行為進行分類，主要區分為存1安全故障與存0安全故障，並使用資料位元反轉技術將故障順利遮蔽，舉例來說，一個固定於邏輯1的故障，在資料儲存時永遠存取邏輯1，即可不讓故障被激發，以節省錯誤更正碼的保護能力。本篇也提出了致命細胞取代技術，致命細胞意指某些記憶體細胞因製程變異而產生阻值變化，隨著寫入次數增長，將引發資料讀取錯誤，因此需藉由備用細胞來取代以達到修復的效果。另外，記憶體中各個編碼字的錯誤數量也有所不同，因此上述的資料位元反轉與致命細胞取代技術，皆配置了漸進式內容定址記憶體，其可針對編碼字中不同數量的硬錯誤與致命細胞進行修復，而本篇也結合了修正餘度的概念，避免系統效能的損耗，當修正餘度抵達臨限值時，才得以啟動本篇技術以有效保護電阻式記憶體。
本研究實現了適應性容錯技術之超大型積體電路，並對一個64 MB的電阻式記憶體進行本方法的修復率、良率、可靠度與硬體成本分析，依實驗結果可知，本篇技術相比記憶體只配置修正能力為3的BCH碼，修復率最高可提升約86%，而在原始良率為0.85時，有效良率最低也能維持在99.7%，可靠度於310,000小時還能保持在 97% 以上，額外增加的硬體成本幾乎不到0.3%。

Due to the advance of process technology, mobile devices and Internet on Things (IOT) are being developed rapidly. Therefore, the demand on Non-Volatile Memory (NVM) keeps increasing steadily. Among the emerging NVM, the resistive memory (RRAM) has the features of lower power consumption, faster operation speed, and smaller core area than flash memory. Moreover, its inherent physical structure can perform matrix operations easily. RRAM is also widely used in the area of Artificial Intelligence (AI). Because the fabrication technology of RRAM is still immature, it would cause serious endurance and yield degradation. Error Correction Code (ECC) is commonly used to solve this problem. However, the errors in RRAM will accumulate during the lifetime. Eventually, the number of errors in a codeword will exceed the protection capability of the adopted ECC. The memory then could not be corrected successfully.
In order to solve the above problems, this thesis reclassify the faults into 1-safe fault and 0-safe fault bases on the fault behaviors of RRAM cells and the Data Bit Inversion (DBI) technique is proposed for fault masking. For example, if a RRAM cell stucks at logic 1, we can always access the cell with logic 1. The fault behavior will not be activated and it can save the protection capability of ECC. This thesis also proposes the Fatal Cell Replacement (FCR) technique. Fatal cell means some memory cells have resistance variation due to the process variation with the increasing of writing cycles. The memory cells will incur data errors when they are being read. They have to be replaced with spare cells. Since the number of errors in each codeword are different, so the proposed DBI and FCR techniques are both equipped with the progressive Content Address Memory (CAM). It can repair different numbers of hard errors or fatal cells in a codeword. This thesis also combines the concept of Correction Slack (CS) to prevent the losses of system performance. When the CS is below the defined threshold, the proposed techniques can be activated to protect RRAM effectively.
The VLSI architecture of the proposed techniques has been implemented. We also analyze the repair rate, yield, reliability and hardware overhead for a 64MB RRAM. According to experimental results, comparing our proposed technique with the memory just equipped with BCH code which correction capability is 3, the repair rate can be increased up to 86%, while the original yield is 0.85, the effective yield can remain about 99.7% in the worst case. The reliability can achieve above 97% at 310,000 hours. The extra hardware overhead is less than 0.3%.

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