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研究生: 林政安
Zheng-An Lin
論文名稱: 單相二極體箝位式五階換流器研製
Study and Implementation of a Single-Phase Diode-Clamped Five-Level Inverter
指導教授: 劉益華
Yi-Hua Liu
謝耀慶
Yao-Ching Hsieh
口試委員: 邱煌仁
Huang-Jen Chiu
林景源
Jing-Yuan Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 57
中文關鍵詞: 獨立運轉二極體箝位式多階換流器正弦脈波寬度調變電容電壓平衡技術
外文關鍵詞: Stand-alone, diode-clamped, multilevel inverter, sinusoidal pulse-width-modulation, switched-capacitor charge equalization technique
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本論文主旨在研製一台獨立運轉(Stand-alone)的單相二極體箝位式五階換流器,利用多階的架構來分散降低在功率開關上的跨壓。為提供適當的電流路徑及功率開關的電壓箝位,此架構需要相當數量的二極體。雖然五階電壓輸出的電壓諧波已較方波或三階電壓輸出低,仍需透過輸出二階低通濾波器,以減少輸出的諧波分量。在控制方面,開關控制信號採用正弦脈波寬度調變信號(Sinusoidal Pulse-Width-Modulation, SPWM),透過振幅調變指數來達到所需的輸出電壓,而頻率調變指數及取樣週期的考量則會影響輸出波形的失真狀況。由於換流器的動作會使得輸入電容電壓不平衡,所以本文也採用電容電壓平衡技術來改善。
本論文實際完成一台輸出功率630 W具有電容電壓平衡技術的原型電路,輸入端電壓為800 V,輸出端電壓為230 V,並以數位信號處理器來實現數位控制,在不同負載下效率均在90%以上。


In this thesis, a stand-alone single-phase diode-clamped five-level inverter is studied and implemented. This prototype circuit makes the input voltage shared by series-connected switching devices. Besides, this topology needs clamped diodes to clamp the voltage on the MOSFETs. Although the output voltage harmonics of five-level inverter are much lower than those of three-level or square wave output inverters, a second-order low pass filter is still necessary to attenuate the switching harmonics. On the other hand, the control signals of the power devices are generated by sinusoidal pulse-width-modulation (SPWM). The desired output voltage can be modulated by the amplitude modulation index; while the frequency modulation index as well as the sampling period will influence the distortion factor of the output waveform. The circuit operation naturally causes the input capacitor voltages unbalance. Accordingly, a switched-capacitor charge equalization technique is implemented to solve the imbalance problem.
A prototype circuit with the switched-capacitor equalizer has been built and tested successfully in this thesis. The circuit is with rated power of 630 W, 800 V input voltage, and 230 V output voltage. A digital-signal processor chip is used to realize the controller of this inverter. The measured efficiency is always higher than 90% within the overall range of load conditions.

摘 要 i Abstract ii 誌 謝 iii 目 錄 iv 圖索引 vii 表索引 ix 第一章 緒論 1 1.1 前言 1 1.2 研究動機與目的 2 1.3 論文內容架構 3 第二章 多階換流器介紹 4 2.1 二極體箝位式多階換流器介紹 4 2.1.1 二極體箝位式多階換流器開關動作真值表 5 2.1.2 二極體箝位式多階換流器架構特性 5 2.2 飛輪電容式多階換流器介紹 6 2.2.1 飛輪電容式多階換流器開關動作真值表 7 2.2.2 飛輪電容式多階換流器架構特性 8 2.3 層疊式全橋多階換流器介紹 9 第三章 單相二極體箝位式五階換流器硬體架構設計 12 3.1 單相二極體箝位式五階換流器簡介 12 3.2 單相二極體箝位式五階換流器電路動作分析 15 3.2.1 區間一(t1 ≤ t < t2) 16 3.2.2 區間二(t2 ≤ t < t3) 17 3.2.3 區間三(t4 ≤ t < t5) 19 3.3 電路參數設計與考量 21 3.3.1 功率開關選用 22 3.3.2 箝位二極體選用 23 3.3.3 輸出低通濾波器設計 23 3.4 驅動電路設計 26 3.4.1 驅動IC簡介 26 3.4.2 參數設計 28 3.4.3 隔離電源選用 29 第四章 數位控制器 30 4.1 數位信號處理器介紹 30 4.1.1 TMS320F28035簡介 30 4.1.2 ePWM模組 33 4.1.3 PLL模組 34 4.2 韌體流程規劃 35 4.3 正弦脈波寬度調變信號 37 4.3.1 ePWM參數設計 37 4.3.2 SPWM參數設計 40 4.4 電容電壓平衡技術 42 4.4.1 電容電壓平衡電路動作分析 42 4.4.2 電容電壓平衡電路參數設計 45 第五章 實驗結果與波形 46 5.1 實驗波形圖 46 5.1.1 單相二極體箝位式五階換流器實驗波形圖 47 5.1.2 電容電壓平衡電路實驗波形圖 49 5.2 實測數據 50 第六章 結論與未來展望 51 6.1 結論 51 6.2 未來展望 51 參考文獻 53

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