閾值邏輯閘是函式表示的一種潛在元件。近年來隨著納米設備的發
展，可用在許多數學模型中。本篇改進了基於查找表分析流程中，映射
閾值邏輯從剪切當中用傳統選擇方法替換子網路的議題，並用最少的
閘數建立閾值邏輯網路。現有基於查找表閾值邏輯網路的方法考慮在
多個網路結構中分析，延長了數倍的分析時間。在這篇論文中，我們提
供一個基於快速指派最佳剪切的閾值邏輯網路分析方法，並進一步用
一個簡易的優化提升成果。實驗結果顯示，藉由我們的方法可以進一步
提升分析的時間和結果

Threshold Logic Gate (TLG) is a function representation potentially capable
of describing neuron behaviors. With advancements in nano-scale devices recently,
several mathematical TLG models can be implemented. In this thesis, we improve
the LUT-based synthesis
ow on threshold logic mapping issue that replaces sub-
networks in a traditional selection between cuts, and constructs the threshold logic
network (TLN) with minimal gate count. Existing LUT-based TLN algorithm per-
forms synthesis on several structural networks, which results in additional analysis
time. Therefore, we present an ecient TLN synthesis method based on our BestCut
assignment to reduce mapping phases and further improve by a simple optimization.
The experimental results indicate that our algorithm can improve TLN synthesis in
both solution quality and run time.

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