簡易檢索 / 詳目顯示

研究生: 劉秉融
Ping-Jung Liu
論文名稱: 穿隧型場效多晶矽薄膜電晶體之研究
Study of Tunneling-Field-Effect Poly-Si Thin-Film-Transistors
指導教授: 莊敏宏
Miin-Horng Juang
口試委員: 黃柏仁
none
徐世祥
none
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 英文
論文頁數: 79
中文關鍵詞: 場效電晶體穿透式薄膜
外文關鍵詞: Tunneling Field Effect Transistor
相關次數: 點閱:239下載:1
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

隨者電子產業的進步,傳統型金氧半電晶體在微型化之後面臨一些可靠度問題,例如短通道效應、熱載子效應、閘極引起位障降低效應。穿隧型場效電晶體在高度微型化可以提供較小的短通道效應、小的熱載子效應以及降低閘極引起位障降低。較可以解決因微型化而造成的可靠度問題。
儘管穿隧型場效電晶體能改善傳統金氧半電晶體的缺點,但是還是面臨一些需要被解決的問題。此論文目的就是透過元件結構的改變以及相關參數模擬分析來實踐獲得高性能的穿透式場效電晶體。關於新元件結構,主要是在源極區外側形成相反摻雜之口袋區域,並改變其離子佈植的劑量或是能量。從模擬分析的結果來看,元件結構的新設計確實較傳統穿隧型場效電晶體之元件有較佳的性能。
由於穿隧型場效電晶體改善傳統型金氧半電晶體因微型化所產生的漏電流問題,並且可以像傳統型金氧半電晶體依樣用於邏輯電路而且製成步驟並沒有太多改變,因此改良之穿隧型場效電晶體可用來當作傳統型金氧半場效電晶體在未來應用上理想的替代性元件。


In the progress of the electronics industry, the scale down of conventional metal oxide semiconductor thin film transistor (MOSFET) will emerge some reliability problems, such as short-channel effect, hot- carrier effect and drain-induce barrier lowering (GIDL). When scale down of tunneling-field-effect transistor, it can make lower short-channel effect, hot-carrier effect and drain-induce barrier lowering. It can solve the reliability problems that it is scaled down.
Although tunneling-field effect transistor (TFET) can improve disadvantages of conventional MOSTFT, some issues of TFET are still need to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. Above this new device structure, a counter-doping pocket region enclosing the source region is formed. The performance of device is really improved by changing different dose and energy. From the simulation results, the newly designed TFET structures do have better performance than the conventional TFET.
TFET improves the leakage current problem of conventional MOSTFT that is produced in high scaling fabrication. Since there are not too many additional process steps compare with MOSFET, the new designed of TFET is an advancing device instead of MOSTFT in the future.

Abstract (Chinese)………………………………………………………...I Abstract………………………………………………………………….III Acknowledgement (Chinese)…………………………………………….V Contents…………………………………………………………………VI Table Lists……………………………………………………………..VIII Figure Captions…………………………………………………………IX Chapter 1 Introduction……………………………………………………1 1-1 Conventional MOSFET device……………………………………2 1-1-1 Short-channel effects………………………………………..2 1-1-2 Drain-induced barrier lowering (DIBL)…………………….3 1-1-3 Hot-carrier effect……………………………………………4 1-1-4 Gate-induced-Drain leakage (GIDL)……………………….5 1-2 Conventional TFET device………………………………………..5 1-2-1 TFET device operating principle……………………………5 1-3 Motivation…………………………………………………………6 1-4 Thesis organization………………………………………………...7 Chapter 2 Device Scheme……………………………………………….12 2-1 Conventional poly-Si MOSFET………………………………….13 2-2 Conventional poly-Si TFET……………………………………...15 2-3 Pocket poly-Si TFET……………………………………………..17 Chapter 3 Results and discussion……………………………………….31 3-1 The influence by the pocket implantation of energy and dose...…31 3-1-1 The pocket implantation of different energy and low dose..31 3-1-2 The pocket implantation of different energy and high dose.35 3-1-3 The pocket implantation of the same energy and different dose………………………………………………………...37 3-1-4 Summary…………………………………………………...38 3-2 The influence of different channel length………………………..56 Chapter 4 Conclusions…………………………………………………..61 Reference………………………………………………………………..62

[1] Nirschl Th, Wang P-F, Webe C, Sedlmeir J, Heinrich R, and Kakoschke R, “The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes.”, IEDM technical digest, pp.195-198, (2004).
[2] S.M Sze and KWOK K. NG, “PHYSICS OF SEMICONDUCTOR DEVICES”, Third Edition, p.328-332, (2007).
[3] S.M Sze and KWOK K. NG, “PHYSICS OF SEMICONDUCTOR DEVICES”, Third Edition, p.333-335, (2007).
[4] S.M Sze and KWOK K. NG, “PHYSICS OF SEMICONDUCTOR DEVICES”, Third Edition, p.335-336, (2007).
[5] S.M Sze and KWOK K. NG, “PHYSICS OF SEMICONDUCTOR DEVICES”, Third Edition, p.338, (2007).
[6] Shockley W. and Hopper WW, “The surface controlled avalanche transistor”, IEEE Tran. Electron Device, Vol.11, No.11, p.535, (1964).
[7] Reddick W.M. and Amaratunga G.A.J, “Gate controlled surface tunneling transistor”, High Speed Semiconductor Devices and Circuits, Vol.7, No. 9, pp.490-497, (1995).
[8] Banerjee S, Richardson W, Coleman J, and Chatterejee A, “A new three-terminal tunnel device”, IEEE Electron Device Letters, Vol.8, No. 8, pp.347–349, (1987).
[9] Koga J. and Toriumi A., “Three-terminal silicon surface junction tunneling device for room temperature operation”, IEEE Electron Device Letters, Vol. 20, No.10, pp.529-531, (1999).
[10] Bhuwalka K.K., Schulze J., and Eisele I., “Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering”, IEEE Tran. Electron Device, Vol.52, No.5, pp.909-917, (2005).
[11] Uemura T. and Baba T., “Direct gate-controlled NDR characteristics in surface tunnel transistor”, Device Research Conference, Vol.20, No.22, pp.65-66, (1994).
[12] Hansch W., Fink C., Schulze J., and Eisele I., “A vertical MOS-gated Esaki tunneling transistor in silicon”, Thin Solid Films, p.369 and pp.387-389, (2000).
[13] Tehrani S., Shen J., Goronkin H., Kramer G., Tsui R., and Zhu T.X., “Resonant interband tunneling FET”, IEEE Electron Device Letters, Vol.16, No.12, pp.557-559, (1995).
[14] Aydin C, Zaslavsky A, Luryi S, Cristoloveanu S, Mariolle D
and Fraboulet D, “Lateral interband tunneling transistor in silicon-insulator” Appl Phys Lett, Vol.84, No.10, pp.1780-1782, (2000).
[15] Kawaura H., Sakamoto T., and Baba T. ,“Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal oxide semiconductor field effect transistors.” , Appl Phys Lett, Vol.76, No.25, pp.3810-3812, (2000).
[16] Wang P-F, Nirschl Th, Schmitt-Landsiedel D, and Hansch W, “Simulation of the Esaki-tunneling FET.”, Solid-State Electron, pp.1131, (2003).
[17] International technology road-map for semiconductor (ITRS), Available from: http://public.itrs.net
[18] Woo Young Choi, “Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors”, Japanese Journal of Applied Physics, Volume 49, Issue 4, pp. 04DJ12-04DJ12-3, (2010).

QR CODE