本篇論文提出了兩個注入式鎖定除頻器與一個低功耗左手雙共振振盪器電路之研究。首先提出了用線性混波技術實現的寬鎖頻範圍的除四注入式鎖定除頻器。第二個晶片展現了通過增強二階諧波訊號完成的寬鎖頻範圍除三注入式鎖定除頻器。最後，我們提出了一個高性能的雙頻帶CMOS左手共振壓控振盪器；以上三個電路都實現於台積電(TSMC) 0.18um CMOS製程。
第一顆晶片展現了用線性混波技術實現的寬鎖頻範圍的新式除四注入式鎖定除頻器。當注入電晶體的汲極與源極偏壓為1伏特，而附加功率為0 dBm時，這顆除四注入式除頻器的除頻範圍大小為7.4 GHz，注入鎖定訊號範圍為7.2 GHz到14.6 GHz，除頻比例為67.89%。晶片面積為0.929×0.841毫米平方，實現於台積電(TSMC)0.18um製程。
第二顆晶片為一個寬鎖定範圍注入鎖定式的新式除三除頻器，使用台積電(TSMC) 0.18 um製程製作而成。傳統的諧波混波注入式除三除頻器除頻的範圍很小，而這篇文章展現了一個用提升二階諧波訊號強度技術完成的寬除頻範圍的注入鎖定式除三電路設計。當這個除三注入鎖定除頻器的汲極與源極偏壓為1伏特，在注入訊號強度為0 dBm時，除頻範圍為4 GHz，注入鎖定訊號範圍為6 GHz至10 GHz(50%)。此晶片的大小為0.822×0.864毫米平方，核心功率消耗為7.72毫瓦。這個提出的電路是以交叉耦合的壓控振盪器為基礎所完成。
最後，文章提出了一個可以操作在低電壓、低相位雜訊的Class-C架構的左手共振壓控振盪器。這個雙頻帶壓控振盪電路實現於台積電(TSMC)0.18um製程，晶片面積為0.749×0.527毫米平方。此篇壓控振盪器可以產生高頻帶6.09~6.21 GHz與低頻帶4.04~4.36 GHz的差動訊號，而整體的Figure Of Merit (FOM)值為高（低）頻190.15(187.24) dBc/Hz，供應電壓為0.65伏特，功耗為1.495毫瓦。這個壓控振盪器使用兩組左手共振諧振電路做串聯，諧振共振腔與交叉耦合電晶體對並聯以抵銷諧振共振腔的損耗。

This thesis presents two Injection-Locked Frequency Dividers (ILFDs) and one VCO which using Left-Hand resonator. First one is a wide locking range Injection-Locked Frequency Divider by 4 designed with linear mixer technique. The second one is a wide locking range divide-by-3 Injection-Locked Frequency Divider through enhanced 2nd Harmonic. Finally, we present a high-performance CMOS left-handed voltage-controlled oscillator(LH VCO) with two frequency bands, above circuits are fabricated in the TSMC 0.18 um CMOS process.
Firstly, we present a novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in this thesis. The thesis shows a wide locking range divide-by-4 ILFD designed with linear mixer technique. At the drain-source bias of 1 V, at the incident power of 0 dBm, the locking range of the divide-by-4 ILFD is 7.4 GHz, from the incident frequency 7.2 GHz to 14.6 GHz, the percentage is 67.89%. A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the thesis and was implemented in the TSMC 0.18 um 1P6M CMOS process.
Secondly, a novel divide-by-3 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18 μm 1P6M CMOS process. Conventional harmonic mixer divide-by-3 ILFD has limited locking range, this thesis shows a wide locking range divide-by-3 ILFD designed with enhanced 2nd harmonic technique. At the drain-source bias VDD of 0.8V and at the incident power of 0 dBm, the locking range of the divide-by-3 is 4GHz, from the incident frequency 6 GHz to 10 GHz, the percentage is 50%. The core power consumption is 7.72 mW. The die area is 0.939 ×0.885 mm2. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator (VCO).
Finally, the thesis proposes a low power, low phase noise Class-C CMOS voltage-controlled oscillator (VCO) using a left-handed (LH) LC network and a switching/tuning varactor pair. The proposed dual-band VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and the die area of the oscillator is 0.527 × 0.749 mm2. The VCO can generate differential signals in the high (low)-band frequency range of 6.09~6.21(4.04~4.36) GHz. The measured high (low)-band figure of merit (FOM) is -190.15 (-187.64) dBc/Hz. The core power consumption is 1.495mW. The VCO uses two units of LH LC resonator stacked in series, and the LC resonator is in shunt with a pair of cross-coupled transistors to compensate for the loss of LC resonator.

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