近年來，超大型積體電路 (VLSI) 技術的快速發展使得電晶體的數量與記憶體細胞密度顯著增加，這個結果已經嚴重威脅到記憶體陣列的良率與可靠度，使得良率明顯下降。因此故障分散 (Fault Scrambling) 技術被提出，可有效改善良率。故障分散技術是將錯誤細胞分散至不同編碼字中，讓每一個編碼字最多只有一個故障細胞，因此，單錯誤更正雙錯誤偵測碼就可以改正編碼字進而改善修復率。但故障分散技術必須使用分散控制字，分散控制字決定分散之效率，而產生控制字之演算法因複雜度太高，通常以軟體實現，尚無有效之演算法適合於硬體實現。
而本篇提出啟發性 (Heuristic) 分散分析演算法，此方法可容易實現於內建電路，並計算出控制字，而內建分散分析電路在此篇提出並加以實現，內建分散分析電路可容易結合於現代普遍之內建自我修復架構。此外本篇所提出之無結合內建自我修復之內建分散分析架構可節省內建自我修復電路以及記憶體備用元件之硬體成本，並且可達到良好的修復效果。依據本篇所開發模擬器之模擬結果，利用混合型分散技術可達到九成的修復率，並與軟體實現之分散分析比較，所提出電路之修復率下降微小，內建分散分析電路可達到軟體窮盡化分析之結果。而硬體成本之比較，所提出之內建分散分析電路只增加至多不到2% 之硬體成本，因此根據實驗之結果，內建分散分析電路在可忽略的硬體成本之下，亦可得到良好的修復率。

In recent years, very-large-scale integration (VLSI) technology continues to progress very fast. The number of transistors and the density of embedded memories are also increasing rapidly. This result threats the yield and the reliability of embedded memories seriously. Therefore, fault scrambling technique is proposed to improve the yield of embedded memories effectively. Fault scrambling technique is considered a promising way to distribute faulty bits into different codewords such that the number of faulty cells in each codeword is below the protection capability of the EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the scrambling control words and the algorithm for generating control word is too complex to implement in hardware.
Therefore, we propose a heuristic algorithm suitable for built-in implementation for the evaluation of control words based on the hardware limitation. The corresponding built-in scrambling analysis (BISA) circuit is also proposed. The BISA module can be easily integrated into the conventional built-in self-repair (BISR) module. In addition, we propose a new architecture with BISA to improve yield without BISR and spare elements. It can save the extra hardware overhead of BISR and spare elements and the yield can achieve more than 90%.
According to experimental results, the repair rate is close to software-based exhaustive analysis and the hardware overhead of the BISA is only about 2%. The result shows that the proposed BISA can improve the repair rate significantly with negligible hardware overhead.

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