簡易檢索 / 詳目顯示

研究生: 林勇翔
Yung-Hsiang Lin
論文名稱: 動態調整寫入緩衝及映射快取之記憶體分配以降低快閃記憶體的寫入操作
Dynamic Memory Allocation for Write Buffer and Mapping Cache to Reduce Write Operations in NAND Flash Memory
指導教授: 吳晋賢
Chin-Hsien Wu
口試委員: 張立平
Li-Pin Chang
張原豪
Yuan-Hao Chang
陳雅淑
Ya-Shu Chen
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 52
中文關鍵詞: 快閃記憶體快閃記憶體轉換層動態記憶體分配迴歸分析緩衝機制
外文關鍵詞: NAND Flash Memory, Flash translation layer, Dynamic Memory Allocation, Regression Analysis, Buffer Mechanism
相關次數: 點閱:157下載:10
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 快閃記憶體(NAND Flash Memory)有著體積小、功耗低、抗震、存取速度快等優點,並隨著移動設備的興起,逐漸成為用戶市場的主流儲存媒介。不過快閃記憶體也有先天的限制,例如: 無法覆寫、不對稱的寫入與抹除單位、有抹除次數的限制…等,因此衍生出一套快閃記憶體轉換層來有效率地管理NAND Flash,並利用RAM維護一個邏輯位址到實體位址的映射表,如此一來可以快速地修改映射資訊。此外,為了降低寫入操作,快閃記憶體轉換層與主機端之間通常會使用RAM建立一套寫入緩衝機制以延長快閃記憶體的使用壽命。基於硬體的共同性,本篇論文提出一個動態配置記憶體的方法,分配映射表與緩衝的記憶體大小,以降低NAND Flash的寫入量。最後實驗顯示,我們的動態調整記憶體機制在大多數Workload下都逼近取樣之最佳靜態記憶體配置的寫入量,與最多寫入量之靜態記憶體配置相比,平均降低了近27%的寫入。


    NAND Flash Memory has some advantages of small size, low power consumption, shock resistance, and fast access speed. With the rise of mobile devices, it gradually becomes the main storage medium in the user market. However, flash memory also has its limitations, such as inability to overwrite, asymmetric writing and erasing units, restrictions on the number of erasing ...etc. Therefore, flash translation layer(FTL) is derived to manage flash memory effectively. It uses RAM to maintain a mapping table for storing information of logical address to physical address. Moreover, in order to reduce write operation, a write buffer will be established between host layer and FTL layer to prolong the lifetime of flash memory. Based on using the same hardware resource(RAM), this paper proposes a method of dynamic memory allocation, which allocates the memory size of the mapping table and write buffer to reduce write operation. Finally, experiments show that under most workloads our dynamic memory allocation method approaches lowest write number from the static memory allocation we sampled. Compared with the static memory allocation with the highest write number, our method reduces 27% number of writes on average.

    中文摘要 I Abstract II 目錄 III 第一章 緒論 1 1.1 前言 1 1.2 論文架構 3 第二章 環境背景 4 2.1 快閃記憶體儲存單元 4 2.2 現今SSD架構說明 5 2.3 Cache/Buffer Management 6 2.3.1 LRU 6 2.3.2 PR-LRU 7 2.4 Flash Translation Layer 8 2.4.1映射機制介紹 9 2.4.2 DFTL 10 2.4.3 HCFTL 11 2.5 機器學習:非線性回歸 12 第三章 研究動機與相關研究 13 3.1 實驗動機 13 3.2 相關研究 14 第四章 研究方法 16 4.1方法架構 16 4.1.1 記憶體分配概觀 16 4.1.2 方法架構 17 4.2 Write Buffer Predictor 18 4.3 Write Mapping Cache Predictor 21 4.4 Memory Allocator 24 第五章 實驗與結果分析 28 5.1 實驗環境 28 5.2 工作負載 29 5.3 方法參數 30 5.4 實驗結果 31 5.4.1 Financial 32 5.4.2 Systor17 34 5.4.3 Microsoft Research Cambridge 36 第六章 結論 40 參考文獻 41

    [1] Chang, Li-Pin, and Tei-Wei Kuo. "An adaptive striping architecture for flash memory storage systems of embedded systems." Proceedings. Eighth IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE, 2002.
    [2] O'neil, Elizabeth J., Patrick E. O'neil, and Gerhard Weikum. "The LRU-K page replacement algorithm for database disk buffering." Acm Sigmod Record 22.2 (1993): 297-306.
    [3] Shasha, D., and T. Johnson. "2q: A low overhead high performance buffer management replacement algoritm." Proceedings of the Twentieth International Conference on Very Large Databases, Santiago, Chile. 1994.
    [4] Yuan, Youwei, et al. "PR-LRU: A novel buffer replacement algorithm based on the probability of reference for flash memory." IEEE Access 5 (2017): 12626-12634.
    [5] Wu, Michael, and Willy Zwaenepoel. "eNVy: a non-volatile, main memory storage system." ACM SIGOPS Operating Systems Review 28.5 (1994): 86-97.
    [6] Chiang, M-L., and R-C. Chang. "Cleaning policies in mobile computers using flash memory." Journal of Systems and Software 48.3 (1999): 213-231.
    [7] Kim, Jesung, et al. "A space-efficient flash translation layer for CompactFlash systems." IEEE Transactions on Consumer Electronics 48.2 (2002): 366-375.
    [8] Lee, Sang-Won, et al. "A log buffer-based flash translation layer using fully-associative sector translation." ACM Transactions on Embedded Computing Systems (TECS) 6.3 (2007): 18-es.
    [9] Cho, Hyunjin, Dongkun Shin, and Young Ik Eom. "KAST: K-associative sector translation for NAND flash memory in real-time systems." 2009 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 2009.
    [10] Jung, Dawoon, et al. "Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme." ACM Transactions on Embedded Computing Systems (TECS) 9.4 (2010): 1-41.
    [11] Gupta, Aayush, Youngjae Kim, and Bhuvan Urgaonkar. "DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings." Acm Sigplan Notices 44.3 (2009): 229-240.
    [12] Chen, Hao, et al. "HCFTL: A locality-aware page-level flash translation layer." 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019.
    [13] Bates, Douglas M., and Donald G. Watts. Nonlinear regression analysis and its applications. Vol. 2. New York: Wiley, 1988.
    [14] Shim, Hyotaek, et al. "An adaptive partitioning scheme for DRAM-based cache in solid state drives." 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST). IEEE, 2010.
    [15] Pauli Virtanen, Ralf Gommers, Travis E. Oliphant, Matt Haberland, Tyler Reddy, David Cournapeau, Evgeni Burovski, Pearu Peterson, Warren Weckesser, Jonathan Bright, Stéfan J. van der Walt, Matthew Brett, Joshua Wilson, K. Jarrod Millman, Nikolay Mayorov, Andrew R. J. Nelson, Eric Jones, Robert Kern, Eric Larson, CJ Carey, İlhan Polat, Yu Feng, Eric W. Moore, Jake VanderPlas, Denis Laxalde, Josef Perktold, Robert Cimrman, Ian Henriksen, E.A. Quintero, Charles R Harris, Anne M. Archibald, Antônio H. Ribeiro, Fabian Pedregosa, Paul van Mulbregt, and SciPy 1.0 Contributors. (2020)
    [16] "SNIA IOTTA trace repository", 2020, [online] Available: http://iotta.snia.org/.
    [17] Council, Storage Performance. "SPC trace file format specification." (2002).
    [18] Lee, Chunghan, et al. "Understanding storage traffic characteristics on enterprise virtual desktop infrastructure." Proceedings of the 10th ACM International Systems and Storage Conference. 2017.
    [19] Narayanan, Dushyanth, Austin Donnelly, and Antony Rowstron. "Write off-loading: Practical power management for enterprise storage." ACM Transactions on Storage (TOS) 4.3 (2008): 1-23.

    QR CODE