在RF射頻收發機中，頻率合成器的特性非常重要，內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而這其中又以壓控振盪器和注入鎖定除頻器特性為主要電路。壓控振盪器需要低相位雜訊來避免相鄰雜訊訊號經由混波轉換的干擾，壓控振盪器的輸出在經由除頻器來達到降頻的工作，因此除頻器必須具有高的操作頻寬與頻率。本篇論文提出一氮化鎵之振盪器與三種不同的除頻器。
首先，我們探討一個使用穩懋0.25微米製程，來呈現一個使用HEMT之LC迴授網路之振盪器。在使用0.8V供應電壓下，電流為2.5mA，功率消耗為2.52mW，此單端輸出電路在3V之Buffer電壓能夠產生8.85GHz並能夠輸出2.4dBm的輸出功率。在1MHz時候之相位雜訊為-124.8dBc/Hz，計算所得到的FoM為-199.8dBc/Hz，此電路的面積為2×1mm2。
其次，本篇量測一個使用穩懋0.25微米氮化鎵製程之HEMT注入式除二鎖定除頻器，此次的量測數據顯示了此電路在電壓應力測試之後振盪頻率、功率消耗與除頻範圍之變化，此電路的面積為2×1 mm2。
第三，本篇量測一個使用台積電0.18矽鍺微米製程之使用雙交叉電容耦合寬頻直接注入式除二鎖定除頻器，並使用三個電感，其寄生電容能夠與電感當作共振腔使用。在低注入功率時，此除頻器能夠有兩個分開的除頻範圍，在注入功率為0dBm時，則會有一個較寬的除頻範圍。在加入超過此製程所能承受之供應電壓之後，會造成此電路之除頻範圍下降，並使得另一個除頻範圍消失，此電路之晶片面積為0.87 × 0.89 mm2。
最後，本篇量測一個使用台積電0.18微米製程之寬除頻範圍之除二注入鎖定除頻器的頻率變化。此除頻器由三路互感耦合諧振器和一組電容交叉耦合與4階RLC共振腔組成以及一個諧波混波MOSFET，第二級電感是由三路徑電感組成，可經由MOSFET開關。在較高的注入功率時，能夠看得出此除頻器具有兩個分開的除頻範圍，當加入超過此製程所能承受之供應電壓之後，會造成此電路之除頻範圍下降，也會造成另一個除頻範圍消失，此晶片面積為0.67×0.863 mm2。

In the RF transceiver, Frequency synthesizer is very important, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). In order to pursue the most important characteristics performance of VCO and Divider, low-power, low phase noise, wide Locking range, this thesis presents the design GaN HEMT oscillator and Injection-Locked Frequency Dividers (ILFDs).
First, this thesis studies a 0.25um GaN HEMT oscillator with output buffer. The oscillator consists of a HEMT amplifier with an LC feedback network. With the supply voltage of VDD = 0.8 V, the GaN oscillator-core current and power consumption of the oscillator are 3.07 mA and 2.45 mW, respectively. The oscillator can generate single-ended signal at 8.85 GHz and it also supplies output power 2.4 dBm with buffer supply 3.0 V. At 1MHz frequency offset from the carrier the phase noise is -124.8 dBc/Hz, the FoM of the proposed oscillator is -199.8 dBc/Hz. The die area of the GaN HEMT oscillator is 2×1 mm2.
Secondly, this thesis studies the RF property of GaN HEMT divide-by-2 injection-locked frequency dividers (ILFDs) under the off-state stress. The studied ILFD was designed in the WIN 0.25 μm GaN HEMT technology. The stress data shows degraded oscillation frequency and current consumption, the former shifts the ILFD operation range. The occupied chip area of the GaN HEMT ILFD is 2×1 mm2.
Thirdly, this thesis studies the high voltage bias effect on the performance of a wide locking range divide-by-2 with dual capacitive cross-coupled injection-locked frequency divider (ILFD), the studied ILFD was implemented in the TSMC standard 0.18 μm SiGe process. The ILFD with a die area 0.87×0.89mm2 uses three on-chip inductors, which form the resonator with the parasitic capacitor. At low injection power, the ILFD has two non-overlapped locking range, at injection power Pinj=0 dBm it has only one locking range. Over-voltage bias causes the degradation on the low–band locking range of the two non-overlapped locking ranges.
Finally, this thesis studies the high voltage bias effect on the performance of a wide locking range divide-by-2 with dual capacitive cross-coupled injection-locked frequency divider (ILFD) based on transformer-based resonator, the studied ILFD was implemented in the TSMC standard 0.18 μm CMOS process. The ILFD with a die area 0.671×0.863 mm2.

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