In wireless communication systems, frequency synthesizers are used to implement the frequency up/down converting of signal. The voltage-controlled oscillator (VCO) and the injection-locked frequency divider (ILFD) are main blocks of a frequency synthesizer. A good VCO must exhibit a low-phase-noise characteristic to prevent noise in adjacent frequencies from being down-converted or up-converted. The frequency of the output signal of VCO is divided down to the reference signal, and is compared with reference signal by phase frequency detector (PFD) to adjust the output of VCO. Therefore, the frequency divider generally has to have the ability of high frequency operation. The wider locking range is, the better ILFD. Moreover, because of working in wireless applications, the low power consumption is required.
In this thesis, we propose two VCOs and one injection-locked frequency divider. First VCO is a 10-GHz CMOS VCO based on Clapp topology. This VCO is fabricated in TSMC 0.18 m process. The second provides quadrature outputs by using PMOS ring coupling technique. The ILFD can operate in two different modes: divide-by-two and divide-by-three by using transformer to inject signals. The two latter circuits are designed and implemented in the TSMC 0.35 m CMOS technology. Both of the proposed circuits are low-power consumption, suitable for wireless applications.
Firstly, a 10-GHz differential Clapp VCO is presented. By the way, using the coupling between the two inductors of Clapp cores, the proposed circuit has low-power consumption of 2.4 mW at supply voltage of 1.4, and a small size area - 0.491 x 0.675 mm2. The operating frequency of the Clapp VCO can be tuned from 9.83 to 10.42 GHz while the tuning voltage varies from 0.9 to 1.9 V. The phase noise of the proposed circuit is -110.52 dBc/Hz at 1 MHz frequency offset. Figure of merit (FoM) is -187 dBc/Hz.
Secondly, we present a low power consumption quadrature VCO using PMOS ring coupling technique which consists of two n-core VCOs. At 0.8 V supply voltage, the output frequency of the VCO is from 5.14 to 5.34 GHz with 200 MHz tuning range and a phase noise of -113.7 dBc/Hz at 1 MHz offset from the center frequency of 5.24 GHz. Its core current consumption is 1.88 mA and the core power consumption is 1.55 mW. The figure of merit (FoM) of this quadrature VCO is -186 dBc/Hz.
Finally, a multi-modulus CMOS LC-tank ILFD is proposed. It is realized with cross-coupled nMOS oscillator with a LC tank resonator. Two transformers are used to inject the external signals into resonator. By the way changing the phase difference between the differential injection signals, the proposed circuit can operate as a divide-by-two or divide-by-three injection-locked frequency divider. At the supply voltage of 1 V, the power consumption is 3.8 mW. The tuning range of the ILFD is from 4.6 to 5.1 GHz while tuning voltage is from 0 to 1.4 V. The operation ranges are from 9 to 10.3 GHz and 13.6 to 15.3 GHz for divide-by-two and divide-by-three modes, respectively.

In wireless communication systems, frequency synthesizers are used to implement the frequency up/down converting of signal. The voltage-controlled oscillator (VCO) and the injection-locked frequency divider (ILFD) are main blocks of a frequency synthesizer. A good VCO must exhibit a low-phase-noise characteristic to prevent noise in adjacent frequencies from being down-converted or up-converted. The frequency of the output signal of VCO is divided down to the reference signal, and is compared with reference signal by phase frequency detector (PFD) to adjust the output of VCO. Therefore, the frequency divider generally has to have the ability of high frequency operation. The wider locking range is, the better ILFD. Moreover, because of working in wireless applications, the low power consumption is required.
In this thesis, we propose two VCOs and one injection-locked frequency divider. First VCO is a 10-GHz CMOS VCO based on Clapp topology. This VCO is fabricated in TSMC 0.18 m process. The second provides quadrature outputs by using PMOS ring coupling technique. The ILFD can operate in two different modes: divide-by-two and divide-by-three by using transformer to inject signals. The two latter circuits are designed and implemented in the TSMC 0.35 m CMOS technology. Both of the proposed circuits are low-power consumption, suitable for wireless applications.
Firstly, a 10-GHz differential Clapp VCO is presented. By the way, using the coupling between the two inductors of Clapp cores, the proposed circuit has low-power consumption of 2.4 mW at supply voltage of 1.4, and a small size area - 0.491 x 0.675 mm2. The operating frequency of the Clapp VCO can be tuned from 9.83 to 10.42 GHz while the tuning voltage varies from 0.9 to 1.9 V. The phase noise of the proposed circuit is -110.52 dBc/Hz at 1 MHz frequency offset. Figure of merit (FoM) is -187 dBc/Hz.
Secondly, we present a low power consumption quadrature VCO using PMOS ring coupling technique which consists of two n-core VCOs. At 0.8 V supply voltage, the output frequency of the VCO is from 5.14 to 5.34 GHz with 200 MHz tuning range and a phase noise of -113.7 dBc/Hz at 1 MHz offset from the center frequency of 5.24 GHz. Its core current consumption is 1.88 mA and the core power consumption is 1.55 mW. The figure of merit (FoM) of this quadrature VCO is -186 dBc/Hz.
Finally, a multi-modulus CMOS LC-tank ILFD is proposed. It is realized with cross-coupled nMOS oscillator with a LC tank resonator. Two transformers are used to inject the external signals into resonator. By the way changing the phase difference between the differential injection signals, the proposed circuit can operate as a divide-by-two or divide-by-three injection-locked frequency divider. At the supply voltage of 1 V, the power consumption is 3.8 mW. The tuning range of the ILFD is from 4.6 to 5.1 GHz while tuning voltage is from 0 to 1.4 V. The operation ranges are from 9 to 10.3 GHz and 13.6 to 15.3 GHz for divide-by-two and divide-by-three modes, respectively.

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